138 lines
3.5 KiB
C++
138 lines
3.5 KiB
C++
/*
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* (C) Copyright 2010 Quantenna Communications Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __START_INL
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#define __START_INL
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#ifdef __ASSEMBLY__
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#include <config.h>
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#include <asm/arch/platform.h>
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.macro FLUSH_CACHE
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/* flush d-cache */
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mov_s r0, 0x1
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sr r0, [ARC_REG_DC_FLSH]
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1:
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lr r1, [ARC_REG_DC_CTRL]
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and r1, r1, ARC_DC_FLUSH_STATUS_BIT
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brne r1, 0x0, 1b
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/* invalidate i-cache */
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mov_s r0, 0x1
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sr r0, [ARC_REG_IC_IVIC]
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lr r1, [ARC_REG_DC_CTRL]
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.endm
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.macro M_COPY_UBOOT to_addr from_addr
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mov_s r1, \to_addr
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mov_s r2, \from_addr
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mov_s r3, \to_addr + __bss_start - TEXT_BASE
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1:
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ld.ab r0, [r2, 4]
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st.ab r0, [r1, 4]
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brlt r1, r3, 1b
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FLUSH_CACHE
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.endm
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.macro M_DELAY_US us
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mov_s r1, RUBY_FIXED_CPU_CLK
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mov_s r2, \us
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mpy r1, r2, r1
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lsr r1, r1, 20 /* divide by 1024*1024, which is approximately 1000000 */
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1:
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sub.f r1, r1, 1
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bne 1b
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.endm
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.macro M_FILL_BSS
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/* Clear bss */
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mov_s r2, __bss_start
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mov_s r3, __bss_end
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1:
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st.ab 0, [r2, 4]
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brlt r2, r3, 1b
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.endm
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.macro M_GOTO_C_CODE
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/* setup stack pointer */
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mov sp, CONFIG_ARC_STACK_BEGIN
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mov fp, sp
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/* Start C-code */
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jal start_arcboot
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.endm
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.macro M_REMAP_MEM
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/* flip memmap and remap ddr */
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mov r1, RUBY_SYS_CTL_BASE_ADDR
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mov r2, RUBY_SYS_CTL_LINUX_MAP(0x1) | RUBY_SYS_CTL_REMAP(0x3)
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st.di r2, [r1, RUBY_SYS_CTL_MASK - RUBY_SYS_CTL_BASE_ADDR]
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mov r2, RUBY_SYS_CTL_LINUX_MAP(0x1)
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st.di r2, [r1, RUBY_SYS_CTL_CTRL - RUBY_SYS_CTL_BASE_ADDR]
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ld.di r2, [r1, RUBY_SYS_CTL_CTRL - RUBY_SYS_CTL_BASE_ADDR] /* read back to clear pipeline */
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sync /* wait for pipeline to flush */
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.endm
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.macro M_GOTO_IF_EXEC_REMAPPED_SRAM tag
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lr r1, [ARC_REG_PC]
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brlt r1, RUBY_SRAM_BEGIN, 1f
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brgt r1, RUBY_SRAM_BEGIN + RUBY_SRAM_SIZE, 1f
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b \tag
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1:
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.endm
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.macro M_BOOTMODE_CMP val
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mov_s r1, RUBY_SYS_CTL_BASE_ADDR
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ld.di r2, [r1, RUBY_SYS_CTL_CTRL - RUBY_SYS_CTL_BASE_ADDR]
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and r2, r2, 0x3
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cmp_s r2, \val
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.endm
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.macro M_IF_BOOT_FROM_FLASH
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M_BOOTMODE_CMP 0x2
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.endm
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// delay/pulse is 200 * 2.5ns (400mhz) = 500 nS, verified on scope
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#define PHY_RESET_DELAY 200
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.macro M_REMOVE_FROM_RESET
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/* in general case, need to remove ddr and sram from reset
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* We also need to create a reset pulse for external reset pin */
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mov_s r1, RUBY_SYS_CTL_BASE_ADDR
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mov_s r2, RUBY_SYS_CTL_RESET_EXT | RUBY_SYS_CTL_RESET_DDR | RUBY_SYS_CTL_RESET_SRAM
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st.di r2, [r1, RUBY_SYS_CTL_CPU_VEC_MASK - RUBY_SYS_CTL_BASE_ADDR]
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st.di r2, [r1, RUBY_SYS_CTL_CPU_VEC - RUBY_SYS_CTL_BASE_ADDR]
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mov_s r2, RUBY_SYS_CTL_RESET_EXT
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st.di r2, [r1, RUBY_SYS_CTL_CPU_VEC_MASK - RUBY_SYS_CTL_BASE_ADDR]
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/* delay for PHY reset delay */
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mov %lp_count,PHY_RESET_DELAY
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lp 1f
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nop
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1:
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st.di 0, [r1, RUBY_SYS_CTL_CPU_VEC - RUBY_SYS_CTL_BASE_ADDR]
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.endm
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#endif // #ifdef __ASSEMBLY__
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#endif // #ifndef __START_INL
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