188 lines
5.8 KiB
C
188 lines
5.8 KiB
C
/*
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* (C) Copyright 2010 Quantenna Communications Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/******************************************************************************
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* Copyright ARC International (www.arc.com) 2007-2009
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*
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*****************************************************************************/
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/******************************************************************************
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* Copyright Codito Technologies (www.codito.com) Oct 01, 2004
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*****************************************************************************/
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/*
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* linux/arch/arc/mm/cache_arc700.c
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*
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* Copyright (C)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Authors: Amit Bhor, Rahul Trivedi
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* I-Cache and D-cache control functionality.
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* Ashwin Chaugule <ashwin.chaugule@codito.com>
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*/
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#include <command.h>
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#include <common.h>
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#include <asm/arcregs.h>
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#include <asm/cache.h>
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//---------------------------------------------------------------------------------
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/* Please keep it always inlined - it should be safer to use with disable cache function */
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__attribute__((always_inline))
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static inline void _invalidate_icache_all(void)
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{
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/* Invoke Cache INV CMD */
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write_new_aux_reg(ARC_REG_IC_IVIC, 0x1);
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/* read will not complete till the icache inv operation is not over */
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read_new_aux_reg(ARC_REG_IC_CTRL);
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}
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/* Please keep it always inlined - it should be safer to use with disable cache function */
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__attribute__((always_inline))
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static inline void _flush_and_inv_dcache_all(void)
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{
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/* Set the Invalidate mode to FLUSH BEFORE INV */
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write_new_aux_reg(ARC_REG_DC_CTRL, read_new_aux_reg(ARC_REG_DC_CTRL) | ARC_INV_MODE_FLUSH);
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/* Invoke Cache INV CMD */
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write_new_aux_reg(ARC_REG_DC_IVDC, 0x1);
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/* wait for the flush to complete, poll on the FS Bit */
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while(read_new_aux_reg(ARC_REG_DC_CTRL) & ARC_DC_FLUSH_STATUS_BIT);
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}
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//---------------------------------------------------------------------------------
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void invalidate_icache_all(void)
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{
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_invalidate_icache_all();
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}
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void invalidate_icache_range(unsigned long start, unsigned long stop)
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{
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while (start < stop) {
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write_new_aux_reg(ARC_REG_IC_IVIL, start);
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start += ARC_ICACHE_LINE_LEN;
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}
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}
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//---------------------------------------------------------------------------------
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void flush_and_inv_dcache_all(void)
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{
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_flush_and_inv_dcache_all();
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}
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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/* make sure we do not flush here, just invalidate */
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write_new_aux_reg(ARC_REG_DC_CTRL, read_new_aux_reg(ARC_REG_DC_CTRL) & (~ARC_INV_MODE_FLUSH));
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while (start < stop) {
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write_new_aux_reg(ARC_REG_DC_IVDL, start);
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start += ARC_DCACHE_LINE_LEN;
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}
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}
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void flush_and_inv_dcache_range(unsigned long start, unsigned long stop)
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{
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/* make sure we do flush here */
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write_new_aux_reg(ARC_REG_DC_CTRL, read_new_aux_reg(ARC_REG_DC_CTRL) | ARC_INV_MODE_FLUSH);
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while (start < stop) {
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write_new_aux_reg(ARC_REG_DC_IVDL, start);
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start += ARC_DCACHE_LINE_LEN;
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}
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/* wait for the flush to complete, poll on the FS Bit */
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while(read_new_aux_reg(ARC_REG_DC_CTRL) & ARC_DC_FLUSH_STATUS_BIT);
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}
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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while (start < stop) {
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write_new_aux_reg(ARC_REG_DC_FLDL, start);
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start += ARC_DCACHE_LINE_LEN;
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}
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/* wait for the flush to complete, poll on the FS Bit */
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while(read_new_aux_reg(ARC_REG_DC_CTRL) & ARC_DC_FLUSH_STATUS_BIT);
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}
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//---------------------------------------------------------------------------------
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void dcache_disable(void)
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{
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/* Prepare cache for switching off. */
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_flush_and_inv_dcache_all();
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/* Switch cache off */
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write_new_aux_reg(ARC_REG_DC_CTRL, read_new_aux_reg(ARC_REG_DC_CTRL) | ARC_DC_DISABLE);
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}
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void icache_disable(void)
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{
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/* Prepare cache for switching off. */
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_invalidate_icache_all();
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/* Switch cache off */
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write_new_aux_reg(ARC_REG_IC_CTRL, read_new_aux_reg(ARC_REG_IC_CTRL) | ARC_IC_DISABLE);
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}
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//---------------------------------------------------------------------------------
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void dcache_enable(void)
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{
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write_new_aux_reg(ARC_REG_DC_CTRL, read_new_aux_reg(ARC_REG_DC_CTRL) & ~ARC_DC_DISABLE);
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}
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void icache_enable(void)
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{
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write_new_aux_reg(ARC_REG_IC_CTRL, read_new_aux_reg(ARC_REG_IC_CTRL) & ~ARC_IC_DISABLE);
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}
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//---------------------------------------------------------------------------------
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int dcache_status(void)
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{
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return !(read_new_aux_reg(ARC_REG_DC_CTRL) & ARC_DC_DISABLE);
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}
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int icache_status(void)
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{
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return !(read_new_aux_reg(ARC_REG_IC_CTRL) & ARC_IC_DISABLE);
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}
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//---------------------------------------------------------------------------------
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void flush_cache(unsigned long start, unsigned long len)
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{
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unsigned long stop = start+len;
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flush_and_inv_dcache_range(start, stop);
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invalidate_icache_range(start, stop);
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}
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//---------------------------------------------------------------------------------
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