307 lines
9.3 KiB
C
307 lines
9.3 KiB
C
/*
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* (C) Copyright 2006
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* Mindspeed Technologies, Inc. <www.mindspeed.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef _EMAC_H
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#define _EMAC_H
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/********* EMAC registers and masks ******************/
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/* Arm side FIFO control registers */
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#define EMAC_ARM_FIFO_CONTROL 0x0000
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#define EMAC_ARM_FIFO_STATUS 0x0004
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#define EMAC_ARM_FIFO_IACK 0x0004
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#define EMAC_ARM_BIST 0x0008
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#define EMAC_ARM_FIFO_TXSIZE 0x0014
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#define EMAC_ARM_FIFO_TXHIGH 0x0018
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#define EMAC_ARM_FIFO_TXLOW 0x001C
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#define EMAC_ARM_FIFO_RXSIZE 0x0024
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#define EMAC_ARM_FIFO_RXHIGH 0x0028
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#define EMAC_ARM_FIFO_RXLOW 0x002C
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#define EMAC_ARM_TXMAIL0 0x0030
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#define EMAC_ARM_TXMAIL1 0x0034
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#define EMAC_ARM_TXMAIL2 0x0038
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#define EMAC_ARM_TXMAIL3 0x003C
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#define EMAC_ARM_RXMAIL0 0x0040
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#define EMAC_ARM_RXMAIL1 0x0044
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#define EMAC_ARM_RXMAIL2 0x0048
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#define EMAC_ARM_RXMAIL3 0x004C
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#define EMAC_ARM_FIFO_TXDATABYTE 0x4000
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#define EMAC_ARM_FIFO_RXDATABYTE 0x4000
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#define EMAC_ARM_FIFO_TXDATAHWORD 0x8000
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#define EMAC_ARM_FIFO_RXDATAHWORD 0x8000
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#define EMAC_ARM_FIFO_TXDATAWORD 0xC000
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#define EMAC_ARM_FIFO_RXDATAWORD 0xC000
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/* Host side FIFO control registers */
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#define EMAC_HOST_FIFO_CONTROL 0xD000
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#define EMAC_HOST_FIFO_STATUS 0xD004
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#define EMAC_HOST_FIFO_IACK 0xD004
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#define EMAC_HOST_FIFO_TXSIZE 0xD010
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#define EMAC_HOST_FIFO_TXHIGH 0xD014
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#define EMAC_HOST_FIFO_TXLOW 0xD018
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#define EMAC_HOST_FIFO_RXSIZE 0xD020
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#define EMAC_HOST_FIFO_RXHIGH 0xD024
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#define EMAC_HOST_FIFO_RXLOW 0xD028
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#define EMAC_HOST_TXMAIL0 0xD030
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#define EMAC_HOST_TXMAIL1 0xD034
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#define EMAC_HOST_TXMAIL2 0xD038
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#define EMAC_HOST_TXMAIL3 0xD03C
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#define EMAC_HOST_RXMAIL0 0xD040
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#define EMAC_HOST_RXMAIL1 0xD044
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#define EMAC_HOST_RXMAIL2 0xD048
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#define EMAC_HOST_RXMAIL3 0xD04C
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#define EMAC_HOST_FIFO_TXDATA 0xD100
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#define EMAC_HOST_FIFO_RXDATA 0xD100
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/* EMAC Interface */
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#define EMAC_OCR 0xE000
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#define EMAC_ICR 0xE004
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#define EMAC_IF_INT 0xE008
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#define EMAC_OUTPUT 0xE00C
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#define EMAC_RX_STAT_FIFO_DEPTH 0xE010
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#define EMAC_RX_STAT_FIFO_DATA 0xE020
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/* EMAC ARC Table */
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#define EMAC_ARC_TABLE 0xE200
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/* EMAC IP Flow Control CSR */
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#define EMAC_FLOWCTRL_BASE 0xE330
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#define EMAC_FLOWCTRL_PAUSECNT (EMAC_FLOWCTRL_BASE + 0x00)
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#define EMAC_FLOWCTRL_REMPAUSECNT (EMAC_FLOWCTRL_BASE + 0x04)
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/* EMAC IP Control CSR */
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#define EMAC_CTRL_BASE 0xE340
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#define EMAC_MACCTRL (EMAC_CTRL_BASE + 0x00)
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#define EMAC_ARCCTRL (EMAC_CTRL_BASE + 0x04)
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#define EMAC_TXCTRL (EMAC_CTRL_BASE + 0x08)
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#define EMAC_TXSTATUS (EMAC_CTRL_BASE + 0x0C)
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#define EMAC_RXCTRL (EMAC_CTRL_BASE + 0x10)
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#define EMAC_RXSTATUS (EMAC_CTRL_BASE + 0x14)
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#define EMAC_MDDATA (EMAC_CTRL_BASE + 0x18)
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#define EMAC_MDCA (EMAC_CTRL_BASE + 0x1C)
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#define EMAC_ARCENA (EMAC_CTRL_BASE + 0x28)
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#define EMAC_PROMCTL (EMAC_CTRL_BASE + 0x2C)
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#define EMAC_PROMDATA (EMAC_CTRL_BASE + 0x30)
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#define EMAC_MISSCNT (EMAC_CTRL_BASE + 0x3C)
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#define EMAC_RMON_BASE 0xE400
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#define EMAC_CNTDATA (EMAC_RMON_BASE + 0x00)
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#define EMAC_CNTACC (EMAC_RMON_BASE + 0x04)
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#define EMAC_TXRMONIE (EMAC_RMON_BASE + 0x08)
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#define EMAC_RXRMONIE (EMAC_RMON_BASE + 0x0C)
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#define MAX_ARC_ENTRIES 21
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/* ARM fifo control bits */
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#define EMAC_ARM_RXDREQWE 0x0004
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#define EMAC_ARM_TXDREQRE 0x0008
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#define EMAC_ARM_TXCMPLTIE 0x0020
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#define EMAC_ARM_TXFIE 0x0040
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#define EMAC_ARM_TXTHIE 0x0080
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#define EMAC_ARM_RXEIE 0x0100
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#define EMAC_ARM_RXTHIE 0x0200
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#define EMAC_ARM_TXM3IE 0x0400
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#define EMAC_ARM_RXM3IE 0x0800
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#define EMAC_ARM_TXFF_RES 0x1000
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#define EMAC_ARM_RXFF_RES 0x2000
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/* Host fifo control bits */
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#define EMAC_HOST_TXFF_EN 0x0001
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#define EMAC_HOST_HBTXRQ_EN 0x0002
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#define EMAC_HOST_RXFF_EN 0x0008
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#define EMAC_HOST_HBRXRQ_EN 0x0010
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#define EMAC_HOST_TXCP_INH 0x0020
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#define EMAC_HOST_TXEIE 0x0100
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#define EMAC_HOST_TXTHIE 0x0200
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#define EMAC_HOST_TXM3IE 0x0400
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#define EMAC_HOST_RXCMPLTIE 0x0800
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#define EMAC_HOST_RXFIE 0x1000
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#define EMAC_HOST_RXTHIE 0x2000
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#define EMAC_HOST_RXM3IE 0x4000
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#define EMAC_HOST_TRGABORTIE 0x8000
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/* Memory BIST register masks */
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#define EMAC_RXBIST_RESET 0x00000001
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#define EMAC_RXBIST_TEST 0x00000002
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#define EMAC_RXBIST_DBG 0x00000004
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#define EMAC_RXBIST_RESUME_RTN 0x00000008
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#define EMAC_RXBIST_DONE 0x00000010
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#define EMAC_RXBIST_FAIL 0x00000020
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#define EMAC_RXBIST_START_RTN 0x00000040
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#define EMAC_TXBIST_RESET 0x00000100
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#define EMAC_TXBIST_TEST 0x00000200
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#define EMAC_TXBIST_DBG 0x00000400
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#define EMAC_TXBIST_RESUME_RTN 0x00000800
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#define EMAC_TXBIST_DONE 0x00001000
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#define EMAC_TXBIST_FAIL 0x00002000
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#define EMAC_TXBIST_START_RTN 0x00004000
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/* EMAC Operation Controling Register masks*/
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#define EMAC_OCR_ROMCKSE 0x00000003
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#define EMAC_OCR_MDCCKSE 0x0000000C
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#define EMAC_OCR_MIIFDL 0x00000010
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#define EMAC_OCR_MII100L 0x00000020
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#define EMAC_OCR_MIILINKL 0x00000040
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#define EMAC_OCR_MIICONN 0x00000080
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#define EMAC_OCR_TESTMODE 0x00000100
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#define EMAC_OCR_CAMHITL 0x00000200
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#define EMAC_OCR_EMACLPBK 0x00000400
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#define EMAC_OCR_TOSS_INHIBIT 0x00000800
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#define EMAC_OCR_OB_SRESET 0x00001000
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#define EMAC_OCR_IB_SRESET 0x00002000
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#define EMAC_OCR_IP_HRESET 0x00004000
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#define EMAC_OCR_RXPCKSIZE 0x00FF8000
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#define EMAC_OCR_RES24 0x01000000
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#if defined(CONFIG_COMCERTO_515) || defined(CONFIG_COMCERTO_800)
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#define EMAC_OCR_SEL_MII_MODE 0x02000000
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#define EMAC_OCR_SW_SMII_OVRD 0x04000000
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#define EMAC_OCR_SW_SMII_MODE 0x08000000
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#endif
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#define EMAC_OCR_STSFFREQIE 0x10000000
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#define EMAC_OCR_RXSTATIE 0x20000000
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#define EMAC_OCR_TXSTATIE 0x40000000
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#define EMAC_OCR_MIIRQIE 0x80000000
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/* EMAC Input Controlled Register masks */
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#define EMAC_ICR_TXFRMOPT 0x00000007
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#if defined(CONFIG_COMCERTO_515) || defined(CONFIG_COMCERTO_800)
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#define EMAC_ICR_MII100L_POL 0x00000100
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#define EMAC_ICR_MIIFDL_POL 0x00000200
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#define EMAC_ICR_MIILINK_POL 0x00000400
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#define EMAC_ICR_PHYCTRLDIS 0x00008000
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#endif
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/* EMAC I/F Interrupt Register Status masks */
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#define EMAC_INPUT_STSFFREQIRQ 0x10000000 // Read Only
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#define EMAC_INPUT_RXSTATIRQ 0x20000000
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#define EMAC_INPUT_TXSTATIRQ 0x40000000
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#define EMAC_INPUT_MIIRQIRQ 0x80000000
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// EMAC I/F Interrupt Acknowledge Register (same as previsous)
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#define EMAC_INPUT_STSFFREQIAK 0x10000000 // Write Only
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#define EMAC_INPUT_RXSTATIAK 0x20000000
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#define EMAC_INPUT_TXSTATIAK 0x40000000
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/* EMAC Output Status masks */
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#define EMAC_OUT_REV_ID 0x0000000F
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#define REV_SIM 0x0000000E
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#define EMAC_OUT_INTLINK 0x00000010
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#define EMAC_OUT_CAMLOAD 0x00000020
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/* EMAC RX status FIFO data masks */
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#define EMAC_RX_STAT_TYPE 0x18000000
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#define EMAC_RX_STAT_PKTCNT 0x000000FF
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#define EMAC_RX_STAT_IPSTA 0x03FFFFFF
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/* EMAC_MACCTRL bits */
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#define MAC_HALTREQ 0x0001
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#define MAC_HALTIMM 0x0002
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#define MAC_RESET 0x0004
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#define MAC_FULLDUP 0x0008
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#define MAC_LOOPBACK 0x0010
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#define MAC_CONN_MSK 0x0060
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#define MAC_AUTORATE 0x0000
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#define MAC_10MBITS 0x0020
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#define MAC_MIIRATE 0x0040
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#define MAC_LOOP10 0x0080
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#define MAC_LNKCHG 0x0100
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#define MAC_RES9 0x0200
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#define MAC_MISSROLL 0x0400
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#define MAC_RES11 0x0800
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#define MAC_RES12 0x1000
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#define MAC_ENMISSROLL 0x2000
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#define MAC_RES14 0x4000
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#define MAC_LINK10 0x8000
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/* EMAC_ARCCTRL bits */
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#define ARC_STATIONACC 0x0001
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#define ARC_GROUPACC 0x0002
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#define ARC_BROADACC 0x0004
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#define ARC_NEGARC 0x0008
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#define ARC_COMPENA 0x0010
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#define ARC_RESERVED 0xFFE0
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/* EMAC_TXCTRL bits */
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#define TX_EN 0x0001
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#define TX_HALT 0x0002
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#define TX_NOPAD 0x0004
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#define TX_NOCRC 0x0008
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#define TX_FBACK 0x0010
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#define TX_NOEXDEF 0x0020
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#define TX_SDPAUSE 0x0040
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#define TX_MII10 0x0080
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#define TX_EN_UNDER 0x0100
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#define TX_EN_EXDEF 0x0200
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#define TX_EN_LCARR 0x0400
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#define TX_EN_EXCOLL 0x0800
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#define TX_EN_LATECOLL 0x1000
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#define TX_EN_TXPAR 0x2000
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#define TX_EN_COMP 0x4000
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/* EMAC_RXCTRL bits */
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#define RX_EN 0x0001
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#define RX_HALT 0x0002
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#define RX_LONGEN 0x0004
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#define RX_SHORTEN 0x0008
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#define RX_STRIPCRC 0x0010
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#define RX_PASSCTL 0x0020
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#define RX_IGNORECRC 0x0040
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#define RX_RES7 0x0080 // reserved
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#define RX_EN_ALIGN 0x0100
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#define RX_EN_CRCERR 0x0200
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#define RX_EN_OVERFLOW 0x0400
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#define RX_EN_LONGERR 0x0800
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#define RX_RES12 0x1000 // reserved
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#define RX_EN_RXPAR 0x2000
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#define RX_EN_GOOD 0x4000
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#define RX_RES15 0x8000 // reserved
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#define EMAC_MDIO_WRITE 0x400
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#define EMAC_MDIO_BUSY 0x800
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#define EMAC_MDIO_PRESUP 0x1000
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#define EMAC_MDIO_OPERATION_TIMEOUT 10
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#define EMAC_MII_MODE 0
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#define EMAC_FORCE_RMII_MODE 1
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#define EMAC_FORCE_SMII_MODE 2
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#define EMAC_RMII_SMII_MODE 3
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#endif /* _EMAC_H */
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