59 lines
2.1 KiB
C
59 lines
2.1 KiB
C
/*
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* (C) Copyright 2007
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* Mindspeed Technologies, Inc. <www.mindspeed.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Revision 1.2 2007/04/28 Iurii.Golovach
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* the SR status register bits were added
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*/
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#ifndef _SPI_H
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#define _SPI_H
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/* SPI registers */
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#define SPI_CTRLR0 (SPI_BASEADDR + 0x00)
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#define SPI_CTRLR1 (SPI_BASEADDR + 0x04)
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#define SPI_SSIENR (SPI_BASEADDR + 0x08)
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#define SPI_MWCR (SPI_BASEADDR + 0x0c)
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#define SPI_SER (SPI_BASEADDR + 0x10)
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#define SPI_BAUDR (SPI_BASEADDR + 0x14)
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#define SPI_TXFTLR (SPI_BASEADDR + 0x18)
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#define SPI_RXFTLR (SPI_BASEADDR + 0x1c)
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#define SPI_TXFLR (SPI_BASEADDR + 0x20)
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#define SPI_RXFLR (SPI_BASEADDR + 0x24)
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#define SPI_SR (SPI_BASEADDR + 0x28)
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#define SPI_IMR (SPI_BASEADDR + 0x2c)
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#define SPI_ISR (SPI_BASEADDR + 0x30)
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#define SPI_RISR (SPI_BASEADDR + 0x34)
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#define SPI_TXOICR (SPI_BASEADDR + 0x38)
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#define SPI_RXOICR (SPI_BASEADDR + 0x3c)
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#define SPI_RXUICR (SPI_BASEADDR + 0x40)
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#define SPI_MSTICR (SPI_BASEADDR + 0x44)
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#define SPI_ICR (SPI_BASEADDR + 0x48)
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#define SPI_IDR (SPI_BASEADDR + 0x58)
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#define SPI_DR (SPI_BASEADDR + 0x60)
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/* SR - status register bits */
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#define BUSY (1 << 0) /* SSI busy flag, serial transfer in progress */
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#define TFNF (1 << 1) /* Transmit FIFO not full */
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#define TFE (1 << 2) /* Transmit FIFO empty */
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#define RFNE (1 << 3) /* Receive FIFO not empty */
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#define RFF (1 << 4) /* Receive FIFO full */
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#define TXE (1 << 5) /* Transmission error */
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#define DCOL (1 << 6) /* Data collision error */
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#endif /* _SPI_H */
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