551 lines
22 KiB
C
551 lines
22 KiB
C
/*
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* This file contains the configuration parameters for the Atheros AP123 board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* ZyXEL zloader configuration.
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*/
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#ifdef CONFIG_ZYXEL_ZLOADER
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#define CONFIG_ZYXEL_MULTIBOOT
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#define CONFIG_AR7240_GPIO
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#define CONFIG_AR7240_MAX_GPIO_NUM 22
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#define CONFIG_ZGPIO_CMD
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#define CONFIG_ZFLASH_CMD
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#define ZLOADER_EXEC_FAILED_LED_INDICATE \
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do { \
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configure_pio(4, ZGPIO_CONFIG_OUTPUT); \
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configure_pio(14, ZGPIO_CONFIG_OUTPUT); \
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set_pio(4, ZGPIO_LEVEL_LOW); /* Power LED off */ \
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set_pio(14, ZGPIO_LEVEL_HIGH); /* WPS LED on */ \
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} while(0)
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#define CONFIG_BOOT_ZLOADER_CMD "bootm 9f020000"
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#define FACTORY_RESET_BTN_GPIO_NO 18
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#define FACTORY_RESET_BTN_TRIGGER_LEVEL ZGPIO_LEVEL_LOW
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#define UPDATE_RAS_IMG_BTN_GPIO_NO 21 /* WPS button */
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#define UPDATE_RAS_IMG_BTN_TRIGGER_LEVEL ZGPIO_LEVEL_LOW
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#else
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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#endif
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/*-----------------------------------------------------------------------
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* Atheros Source Code Configuration
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*/
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/* See cpu/mips/ar7240/Makefile */
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#define CONFIG_SOC_AG934X 1
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#if !defined(CONFIG_ATH_NAND_FL)
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#define FLASH_SIZE 4
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#endif
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#define CFG_FLASH_SECTOR_SIZE (64*1024)
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#if (FLASH_SIZE == 16)
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#define CFG_FLASH_SIZE 0x01000000 /* Total flash size */
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#elif (FLASH_SIZE == 8)
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#define CFG_FLASH_SIZE 0x00800000 /* max number of sectors on one chip */
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#else
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#define CFG_FLASH_SIZE 0x00400000 /* Total flash size */
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#endif
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#ifndef COMPRESSED_UBOOT
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#define ENABLE_DYNAMIC_CONF 1
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#endif
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#define CONFIG_WASP_SUPPORT 1
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#undef CFG_ATHRS26_PHY
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/* S16 specific defines */
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#define CONFIG_AG7240_GE0_IS_CONNECTED 1
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// PLL Config for different CPU/DDR/AHB frequencies
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#define CFG_PLL_200_200_100 0x00
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#define CFG_PLL_300_300_150 0x01
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#define CFG_PLL_320_320_160 0x02
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#define CFG_PLL_340_340_170 0x03
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#define CFG_PLL_350_350_175 0x04
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#define CFG_PLL_360_360_180 0x05
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#define CFG_PLL_400_400_200 0x06
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#define CFG_PLL_300_300_75 0x07
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#define CFG_PLL_400_400_100 0x08
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#define CFG_PLL_320_320_80 0x09
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#define CFG_PLL_410_400_200 0x0a
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#define CFG_PLL_420_400_200 0x0b
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#define CFG_PLL_80_80_40 0x0c
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#define CFG_PLL_64_64_32 0x0d
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#define CFG_PLL_48_48_24 0x0e
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#define CFG_PLL_32_32_16 0x0f
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#define CFG_PLL_333_333_166 0x10
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#define CFG_PLL_266_266_133 0x11
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#define CFG_PLL_266_266_66 0x12
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#define CFG_PLL_240_240_120 0x13
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#define CFG_PLL_160_160_80 0x14
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#define CFG_PLL_400_200_200 0x15
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#define CFG_PLL_500_400_200 0x16
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#define CFG_PLL_600_400_200 0x17
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#define CFG_PLL_600_500_250 0x18
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#define CFG_PLL_600_400_300 0x19
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#define CFG_PLL_500_500_250 0x1a
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#define CFG_PLL_600_350_175 0x1b
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#define CFG_PLL_600_300_150 0x1c
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#define CFG_PLL_600_550_1_1G_275 0x1d
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#define CFG_PLL_600_500_1G_250 0x1e
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#define CFG_PLL_533_400_200 0x1f
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#define CFG_PLL_600_450_200 0x20
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#define CFG_PLL_533_500_250 0x21
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#define CFG_PLL_700_400_200 0x22
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#define CFG_PLL_650_600_300 0x23
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#define CFG_PLL_600_600_300 0x24
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#define CFG_PLL_600_550_275 0x25
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#define CFG_PLL_566_475_237 0x26
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#define CFG_PLL_566_450_225 0x27
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#define CFG_PLL_600_332_166 0x28
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#define CFG_PLL_600_575_287 0x29
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#define CFG_PLL_600_525_262 0x2a
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#define CFG_PLL_566_550_275 0x2b
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#define CFG_PLL_566_525_262 0x2c
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#define CFG_PLL_600_332_200 0x2d
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#define CFG_PLL_600_266_133 0x2e
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#define CFG_PLL_600_266_200 0x2f
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#define CFG_PLL_600_650_325 0x30
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#define CFG_PLL_566_400_200 0x31
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#define CFG_PLL_566_500_250 0x32
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#define CFG_PLL_600_1_2G_400_200 0x33
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#define CFG_PLL_560_480_240 0x34
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#define CFG_PLL_333_166_166 0x35
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#define CFG_PLL_350_175_175 0x36
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#define CFG_PLL_360_180_180 0x37
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#define CFG_PLL_380_190_190 0x38
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#define CFG_PLL_262_262_131 0x39
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#define CFG_PLL_275_275_137 0x3a
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#define CFG_PLL_200_200_200 0x3b
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#define CFG_PLL_250_250_125 0x3c
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#define CFG_PLL_225_225_112 0x3d
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#define CFG_PLL_212_212_106 0x3e
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#define CFG_PLL_187_187_93 0x3f
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#define CFG_PLL_535_400_200 0x40
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#define CFG_PLL_560_400_200 0x41
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#define CFG_PLL_560_450_225 0x42
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#define CFG_PLL_400_480_240 0x43
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#undef CFG_PLL_FREQ
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#define CFG_PLL_FREQ CFG_PLL_535_400_200
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//#define CONFIG_NR_DRAM_BANKS 2
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// Set this to zero, for 16bit ddr2
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#define DDR2_32BIT_SUPPORT 1
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/* DDR settings for WASP */
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#define CFG_DDR_REFRESH_VAL 0x4270
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#define CFG_DDR_CONFIG_VAL 0xc7bc8cd0
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#define CFG_DDR_MODE_VAL_INIT 0x133
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#define CFG_DDR_EXT_MODE_VAL 0x0
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#define CFG_DDR_MODE_VAL 0x33
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#define CFG_DDR_TRTW_VAL 0x1f
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#define CFG_DDR_TWTR_VAL 0x1e
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#define CFG_DDR_CONFIG2_VAL 0x9dd0e6a8
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#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32 0xff
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#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff
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#if DDR2_32BIT_SUPPORT
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#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32
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#else
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#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16
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#endif
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#define CFG_DDR1_RD_DATA_THIS_CYCLE_VAL 0xffff
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#define CFG_SDRAM_RD_DATA_THIS_CYCLE_VAL 0xffffffff
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/* DDR2 Init values */
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#define CFG_DDR2_EXT_MODE_VAL 0x402
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#if !defined(CONFIG_WASP) && defined(ENABLE_DYNAMIC_CONF)
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#define CFG_DDR_MAGIC 0xaabacada
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#define CFG_DDR_MAGIC_F (UBOOT_ENV_SEC_START + CFG_FLASH_SECTOR_SIZE - 0x30)
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#define CFG_DDR_CONFIG_VAL_F *(volatile int *)(CFG_DDR_MAGIC_F + 4)
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#define CFG_DDR_CONFIG2_VAL_F *(volatile int *)(CFG_DDR_MAGIC_F + 8)
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#define CFG_DDR_EXT_MODE_VAL_F *(volatile int *)(CFG_DDR_MAGIC_F + 12)
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#endif
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//#define CFG_WAH132 1
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/*
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** Parameters defining the location of the calibration/initialization
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** information for the two Merlin devices.
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** NOTE: **This will change with different flash configurations**
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*/
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#define WLANCAL 0x9fff1000
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#define BOARDCAL 0x9fff0000
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#define ATHEROS_PRODUCT_ID 137
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#define CAL_SECTOR (CFG_MAX_FLASH_SECT - 1)
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/*-----------------------------------------------------------------------
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* Board Configuration
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*/
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#define CONFIG_BOARD_AP123 1
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#define CONFIG_BOARD_NAME "AP123"
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/*-----------------------------------------------------------------------
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* CPU Core Configuration
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*/
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#define CONFIG_MIPS32 1 /* MIPS 47Kc CPU core */
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#define CONFIG_MEMSIZE_IN_BYTES
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/*
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* MIPS32 24K Processor Core Family Software User's Manual
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*
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* 6.2.9 Count Register (CP0 Register 9, Select 0)
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* The Count register acts as a timer, incrementing at a constant
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* rate, whether or not an instruction is executed, retired, or
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* any forward progress is made through the pipeline. The counter
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* increments every other clock, if the DC bit in the Cause register
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* is 0.
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*/
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/* Since the count is incremented every other tick, divide by 2 */
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/* XXX derive this from CFG_PLL_FREQ */
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#if (CFG_PLL_FREQ == CFG_PLL_200_200_100)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (200000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_300_300_150)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (300000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_350_350_175)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (350000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_333_333_166)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (333000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_266_266_133)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (266000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_266_266_66)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (266000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_400_400_200) || (CFG_PLL_FREQ == CFG_PLL_400_400_100)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (400000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_320_320_80) || (CFG_PLL_FREQ == CFG_PLL_320_320_160)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (320000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_410_400_200)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (410000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_420_400_200)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (420000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_240_240_120)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (240000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_160_160_80)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (160000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_400_200_200)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (400000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_500_400_200)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (500000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_600_400_200) || (CFG_PLL_FREQ == CFG_PLL_600_450_200) || \
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(CFG_PLL_FREQ == CFG_PLL_600_600_300) || (CFG_PLL_FREQ == CFG_PLL_600_550_275) || \
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(CFG_PLL_FREQ == CFG_PLL_600_332_166) || (CFG_PLL_FREQ == CFG_PLL_600_575_287) || \
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(CFG_PLL_FREQ == CFG_PLL_600_525_262) || (CFG_PLL_FREQ == CFG_PLL_600_332_200) || \
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(CFG_PLL_FREQ == CFG_PLL_600_266_133) || (CFG_PLL_FREQ == CFG_PLL_600_266_200) || \
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(CFG_PLL_FREQ == CFG_PLL_600_650_325) || (CFG_PLL_FREQ == CFG_PLL_600_1_2G_400_200)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (600000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_600_1_2G_400_200)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (600000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_600_500_1G_250)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (600000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_600_550_1_1G_275)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (600000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_600_500_250)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (600000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_600_350_175)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (600000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_600_300_150)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (600000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_533_400_200) || (CFG_PLL_FREQ == CFG_PLL_533_500_250)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (533000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_535_400_200)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (535000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_700_400_200)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (700000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_650_600_300)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (650000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_560_480_240)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (560000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_566_475_237) || (CFG_PLL_FREQ == CFG_PLL_566_450_225) || \
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(CFG_PLL_FREQ == CFG_PLL_566_550_275) || (CFG_PLL_FREQ == CFG_PLL_566_525_262) || \
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(CFG_PLL_FREQ == CFG_PLL_566_400_200) || (CFG_PLL_FREQ == CFG_PLL_566_500_250)
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# define CONFIG_SYS_MIPS_TIMER_FREQ (566000000/2)
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_DCACHE_SIZE (32*1024)
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#define CONFIG_SYS_ICACHE_SIZE (64*1024)
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#define CONFIG_SYS_CACHELINE_SIZE 32
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options
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*/
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SERVERIP 192.168.1.33
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#define CONFIG_IPADDR 192.168.1.1
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#define CONFIG_ETHADDR 00:AA:BB:CC:DD:00
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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#define CONFIG_VERSION_VARIABLE /* keep u-boot version string in environment */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT CONFIG_BOARD_NAME "# " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
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#define CONFIG_SYS_MALLOC_LEN 256*1024
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#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
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#define CONFIG_SYS_MEMTEST_START 0x80200000
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#define CONFIG_SYS_MEMTEST_END 0x83800000
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#define CONFIG_LZMA 1
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#define CONFIG_SYS_INIT_SP_OFFSET 0x1000
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN CFG_LOADER_PART_SIZE
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#undef CONFIG_ENV_IS_NOWHERE
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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/* Assuming nand flash wouldn't use compressed u-boot */
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#ifdef CONFIG_ATH_NAND_FL
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# define CONFIG_SYS_FLASH_BASE 0
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#else
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# define CONFIG_SYS_FLASH_BASE 0x9f000000
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#endif
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#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
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#if (FLASH_SIZE == 16)
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#elif (FLASH_SIZE == 8)
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#else
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#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
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#endif
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#if (CONFIG_SYS_MAX_FLASH_SECT * CFG_FLASH_SECTOR_SIZE) != CFG_FLASH_SIZE
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# error "Invalid flash configuration"
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#endif
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#define CONFIG_SYS_JFFS2_FIRST_BANK 1
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#define CONFIG_SYS_JFFS2_NUM_BANKS 1
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#define CONFIG_ENV_SECT_SIZE CFG_FLASH_SECTOR_SIZE
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#define CONFIG_ENV_SIZE CFG_ENV_PART_SIZE
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_OVERWRITE
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/* CONFIG_ENV_VERSION
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* v1.0: initial version
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* v1.1: add environment variable 'env_readonly' to set partition 'env' as read-only
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* v1.2: rename environment variable 'env_readonly' to 'readonly' for setting
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* partition 'env' & 'RFData' as read-only
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* v1.3: add environment variable 'zld_ver' to record zloader version and put it in
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* kernel command line
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*/
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#define CONFIG_ENV_VERSION "1.3"
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/*-----------------------------------------------------------------------
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* Partition Configuration
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*/
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#undef CONFIG_BOOTARGS
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#ifndef CONFIG_ZYXEL_ZLOADER
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#define __gen_cmd(cmd, offs, file, eraseCmd, writeCmd, eraseSize) \
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#cmd "=tftp ${loadaddr} ${dir}" #file ";" \
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#eraseCmd " " #offs " +" #eraseSize ";" \
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#writeCmd " ${fileaddr} " #offs " ${filesize}\0"
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#define gen_cmd(cmd, offs, file, partSize) \
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__gen_cmd(cmd, offs, file, erase, cp.b, partSize)
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#else
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#define __gen_cmd(cmd, offs, file, eraseCmd, writeCmd, eraseSize) \
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#cmd "=tftp ${loadaddr} ${dir}" #file ";" \
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#eraseCmd " " #offs " " #eraseSize ";" \
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#writeCmd " ${fileaddr} " #offs " ${filesize}\0"
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#define gen_cmd(cmd, offs, file, partSize) \
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__gen_cmd(cmd, offs, file, zflash erase, zflash write, partSize)
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#endif
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#define __gen_img_env_val(name, addr, size) \
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#name "_part_addr=" #addr "\0" \
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#name "_part_size=" #size "\0"
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#define gen_img_env_val(name, addr, size) \
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__gen_img_env_val(name, addr, size)
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#define CFG_LOADER_PART_ADDR CONFIG_SYS_FLASH_BASE
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#ifdef CONFIG_EMBEDDED_KERNEL_IN_ROOTFS
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#define CFG_LOADER_PART_SIZE 0x30000
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#define CFG_ENV_PART_ADDR 0x9f030000
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#define CFG_ENV_PART_SIZE 0x10000
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#define CFG_RFDATA_PART_ADDR 0x9f040000
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#define CFG_RFDATA_PART_SIZE 0x10000
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#define CFG_ROOTFSDATA_PART_ADDR 0x9f050000
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#define CFG_ROOTFSDATA_PART_SIZE 0x60000
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#define CFG_HEADER_PART_ADDR 0x9f0b0000
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#define CFG_HEADER_PART_SIZE 0x10000
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#define CFG_ROOTFS_PART_ADDR 0x9f0c0000
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#define CFG_ROOTFS_PART_SIZE 0x340000
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#define CFG_RAS_PART_ADDR 0x9f0b0000
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#define CFG_RAS_PART_SIZE 0x350000
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#if (CFG_RAS_PART_ADDR!=CFG_HEADER_PART_ADDR) || (CFG_RAS_PART_SIZE!=(CFG_HEADER_PART_SIZE+CFG_ROOTFS_PART_SIZE))
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#error "Wrong address/size of RAS partition!"
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#endif
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#define LOADER_IMG_ENV_VAL gen_img_env_val(loader, CFG_LOADER_PART_ADDR, CFG_LOADER_PART_SIZE)
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#define ENV_IMG_ENV_VAL gen_img_env_val(env, CFG_ENV_PART_ADDR, CFG_ENV_PART_SIZE)
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#define RFDATA_IMG_ENV_VAL gen_img_env_val(rfdat, CFG_RFDATA_PART_ADDR, CFG_RFDATA_PART_SIZE)
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#define RTFSDATA_IMG_ENV_VAL gen_img_env_val(rtfsdat, CFG_ROOTFSDATA_PART_ADDR, CFG_ROOTFSDATA_PART_SIZE)
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#define HEADER_IMG_ENV_VAL gen_img_env_val(hdr, CFG_HEADER_PART_ADDR, CFG_HEADER_PART_SIZE)
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#define ROOTFS_IMG_ENV_VAL gen_img_env_val(rootfs, CFG_ROOTFS_PART_ADDR, CFG_ROOTFS_PART_SIZE)
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#define RAS_IMG_ENV_VAL gen_img_env_val(ras, CFG_RAS_PART_ADDR, CFG_RAS_PART_SIZE)
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#define UPDATE_LOADER_CMD gen_cmd(lu, ${loader_part_addr}, u-boot.bin, ${loader_part_size})
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#define UPDATE_ROOTFS_CMD gen_cmd(lf, ${rootfs_part_addr}, ${img_prefix}rootfs.jffs2, ${rootfs_part_size})
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#define UPDATE_RAS_CMD gen_cmd(lr, ${ras_part_addr}, ras.bin, ${ras_part_size})
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#define IMG_ENV_VAL LOADER_IMG_ENV_VAL ENV_IMG_ENV_VAL RFDATA_IMG_ENV_VAL \
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RTFSDATA_IMG_ENV_VAL HEADER_IMG_ENV_VAL ROOTFS_IMG_ENV_VAL RAS_IMG_ENV_VAL
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#define UPGRADE_IMG_CMD UPDATE_LOADER_CMD UPDATE_ROOTFS_CMD UPDATE_RAS_CMD
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#define ROOTFS_MTD_NO "root_mtdblock_no=5\0"
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#define MTDPARTS_DEFAULT "mtdparts=ath-nor0:${loader_part_size}(u-boot),${env_part_size}(env)${readonly},${rfdat_part_size}(RFdata)${readonly},${rtfsdat_part_size}(rootfs_data),${hdr_part_size}(header),${rootfs_part_size}(rootfs)\0"
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#define BOOT_FLASH_CMD "boot_flash=run setmtdparts flashargs addtty addmtd;fsload ${loadaddr} /boot/vmlinux.lzma.uImage;bootm ${loadaddr}\0"
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#define INIT_PROCESS_ENV "/etc/preinit"
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#else
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#define CFG_LOADER_PART_SIZE 0x40000
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#define CFG_ENV_PART_ADDR 0x9f040000
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#define CFG_ENV_PART_SIZE 0x10000
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#define CFG_ROOTFS_PART_ADDR 0x9f050000
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#define CFG_ROOTFS_PART_SIZE 0x230000
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#define CFG_KERNEL_PART_ADDR 0x9f280000
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#define CFG_KERNEL_PART_SIZE 0x160000
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#define CFG_MIB0_PART_ADDR 0x9f3E0000
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#define CFG_MIB0_PART_SIZE 0x10000
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#define CFG_ART_PART_ADDR 0x9f3F0000
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#define CFG_ART_PART_SIZE 0x10000
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#define LOADER_IMG_ENV_VAL gen_img_env_val(loader, CFG_LOADER_PART_ADDR, CFG_LOADER_PART_SIZE)
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#define ENV_IMG_ENV_VAL gen_img_env_val(env, CFG_ENV_PART_ADDR, CFG_ENV_PART_SIZE)
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#define ROOTFS_IMG_ENV_VAL gen_img_env_val(rootfs, CFG_ROOTFS_PART_ADDR, CFG_ROOTFS_PART_SIZE)
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#define KERNEL_IMG_ENV_VAL gen_img_env_val(kernel, CFG_KERNEL_PART_ADDR, CFG_KERNEL_PART_SIZE)
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#define MIB0_IMG_ENV_VAL gen_img_env_val(mib0, CFG_MIB0_PART_ADDR, CFG_MIB0_PART_SIZE)
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#define ART_IMG_ENV_VAL gen_img_env_val(art, CFG_ART_PART_ADDR, CFG_ART_PART_SIZE)
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#define UPDATE_LOADER_CMD gen_cmd(lu, ${loader_part_addr}, u-boot.bin, ${loader_part_size})
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#define UPDATE_KERNEL_CMD gen_cmd(lk, ${kernel_part_addr}, ${img_prefix}vmlinux.lzma.uImage, ${kernel_part_size})
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#define UPDATE_ROOTFS_CMD gen_cmd(lf, ${rootfs_part_addr}, ${img_prefix}rootfs.jffs2, ${rootfs_part_size})
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#define IMG_ENV_VAL LOADER_IMG_ENV_VAL ENV_IMG_ENV_VAL KERNEL_IMG_ENV_VAL ROOTFS_IMG_ENV_VAL MIB0_IMG_ENV_VAL ART_IMG_ENV_VAL
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#define UPGRADE_IMG_CMD KERNEL_IMG_ENV_VAL UPDATE_LOADER_CMD UPDATE_KERNEL_CMD UPDATE_ROOTFS_CMD
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#define ROOTFS_MTD_NO "root_mtdblock_no=2\0"
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#define MTDPARTS_DEFAULT "mtdparts=ath-nor0:${loader_part_size}(u-boot),${env_part_size}(env),${rootfs_part_size}(rootfs),${kernel_part_size}(kernel),${mib0_part_size}(mib0),${art_part_size}(ART)\0"
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#define BOOT_FLASH_CMD "boot_flash=run setmtdparts flashargs addtty addmtd;bootm ${kernel_part_addr}\0"
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#define INIT_PROCESS_ENV "/sbin/init"
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#endif
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#if CONFIG_ENV_ADDR != CFG_ENV_PART_ADDR
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#error "Wrong address of u-boot environment partition"
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#endif
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/* ROOTFS_MTD_NO, MTDPARTS_DEFAULT, BOOT_FLASH_CMD, IMG_ENV_VAL, UPGRADE_IMG_CMD */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"uboot_env_ver=" CONFIG_ENV_VERSION "\0" \
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"img_prefix=pla4231-\0" \
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"loadaddr=80400000\0" \
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"init_process=" INIT_PROCESS_ENV "\0" \
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ROOTFS_MTD_NO \
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"readonly=ro\0" \
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"rootfstype=jffs2\0" \
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"setmtdparts=setenv mtdparts " MTDPARTS_DEFAULT \
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"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock${root_mtdblock_no} rootfstype=${rootfstype} rw ${bootmode} ${zld_ver}\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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BOOT_FLASH_CMD \
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"bootcmd=run boot_flash\0" \
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IMG_ENV_VAL \
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UPGRADE_IMG_CMD \
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"countrycode=ff\0" \
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"serialnum=S100Z47000001\0" \
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"hostname=AP123\0" \
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/*-----------------------------------------------------------------------
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* JFFS2 Filesystem Configuration
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*/
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#define CONFIG_CMD_JFFS2
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//#define CONFIG_CMD_JFFS2_LS
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//#define CONFIG_CMD_JFFS2_FSINFO
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#define CONFIG_JFFS2_PART_OFFSET (CFG_ROOTFS_PART_ADDR-CONFIG_SYS_FLASH_BASE)
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// Default using remaining flash space if you ignore 'CONFIG_JFFS_PART_SIZE'
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#define CONFIG_JFFS2_PART_SIZE CFG_ROOTFS_PART_SIZE
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/*-----------------------------------------------------------------------
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* Networking Configuration
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*/
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#define CONFIG_NET_MULTI
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#define CONFIG_SYS_RX_ETH_BUFFER 16
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//#define CFG_PHY_ADDR 0
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//#define CFG_GMII 0
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#define CFG_MII0_RMII 1
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#define CFG_AG7100_GE0_RMII 1
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#ifndef CONFIG_ZYXEL_ZLOADER
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#define CONFIG_MII
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#define CONFIG_CMD_MII
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#define CONFIG_PHY_GIGE
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#endif
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#define CONFIG_SYS_CONSOLE_INFO_QUIET
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//#define CONFIG_SILENT_CONSOLE
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#define CONFIG_DISABLE_CONSOLE
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/*-----------------------------------------------------------------------
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* PCI Configuration
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*/
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#undef CONFIG_PCI
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#ifdef CONFIG_PCI
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#define CONFIG_SHUTDOWN_PCIE_USB 1
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/* For Merlin, both PCI, PCI-E interfaces are valid */
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#define AR7240_ART_PCICFG_OFFSET 12
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#endif
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/*-----------------------------------------------------------------------
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#ifndef CONFIG_ZYXEL_ZLOADER
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_PING
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#else
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#undef CONFIG_CMD_MEMORY
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#undef CONFIG_CMD_MISC
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#undef CONFIG_CMD_BDI
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#undef CONFIG_CMD_ECHO
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#undef CONFIG_CMD_EDITENV
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#undef CONFIG_CMD_BOOTD
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#undef CONFIG_CMD_LOADB
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#undef CONFIG_CMD_IMI
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#endif
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#undef CONFIG_CMD_CONSOLE
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_ITEST
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_NFS
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#undef CONFIG_CMD_SETGETDCR
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#undef CONFIG_CMD_SOURCE
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#undef CONFIG_CMD_XIMG
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#if TEXT_BASE != 0x9F000000
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#endif
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#endif /* __CONFIG_H */
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