141 lines
3.0 KiB
C++
141 lines
3.0 KiB
C++
/*
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* (C) Copyright 2010 Quantenna Communications Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#ifdef CONFIG_CMD_UC
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#include <asm/arcregs.h>
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#include <asm/arch/platform.h>
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#include "ruby.h"
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.macro UC_TRACE
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ld.di r0, [uc_trace_num]
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add r0, r0, 1
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st.di r0, [uc_trace_num]
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.endm
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.macro UC_TRACE_DONE
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mov r0, 1
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st.di r0, [uc_trace_done]
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.endm
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.macro UC_ENABLE_ARC_INTRS
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/*
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* INT_VECTOR_BASE register on MuC(Ruby) after reset contains 0x0, but internal logic
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* uses start address for vector base (till INT_VECTOR_BASE is resetted) - no need really to setup.
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* INT_VECTOR_BASE register on DSP(Ruby) must be setted to have interrupts work.
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* Having such irregularity it would be better to setup register always.
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*/
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UC_TRACE
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mov r0, UC_ENTRY_SLOT
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sr r0, [ARC_REG_INTR_VEC_BASE]
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/*
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* AUX_IENABLE register after reset has all interrupts enabled - no need to setup,
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* but for safety let's do it.
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*/
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UC_TRACE
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mov r0, 0xFFFFFFFF
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sr r0, [ARC_REG_INTR_ENABLE]
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/* Enable interrupts in STATUS32 register */
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UC_TRACE
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flag STATUS_E1_MASK | STATUS_E2_MASK
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.endm
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.macro UC_ENABLE_INTRS_MUC
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/* Enable external interrupts (Ruby specific) */
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UC_TRACE
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mov r0, 0x0
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st.di r0, [RUBY_SYS_CTL_MUC_ORINT_EN]
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mov r0, 0xFFFFFFFF
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st.di r0, [RUBY_SYS_CTL_MUC_INT_EN]
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/* Enable ARC interrupts */
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UC_ENABLE_ARC_INTRS
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.endm
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.macro UC_ENABLE_INTRS_DSP
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/* Enable external interrupts (Ruby specific) */
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UC_TRACE
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mov r0, 0x0
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st.di r0, [RUBY_SYS_CTL_DSP_ORINT_EN]
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mov r0, 0xFFFFFFFF
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st.di r0, [RUBY_SYS_CTL_DSP_INT_EN]
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/* Enable ARC interrupts */
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UC_ENABLE_ARC_INTRS
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.endm
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.macro UC_DISABLE_DCACHE
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UC_TRACE
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lr r0, [ARC_REG_DC_CTRL]
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or r0, r0, ARC_DC_DISABLE
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sr r0, [ARC_REG_DC_CTRL]
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.endm
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.macro UC_PREPARE_STACK
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UC_TRACE
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mov sp, __uc_stack
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mov fp, sp
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.endm
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.macro UC_RUN_C name
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UC_TRACE
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mov r0, \name
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jl [r0]
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.endm
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.macro UC_INDEFINITE_LOOP
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UC_TRACE
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UC_TRACE_DONE
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1:
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sleep
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UC_TRACE
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b 1b
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.endm
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.macro UC_CODE func_name
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UC_DISABLE_DCACHE
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UC_PREPARE_STACK
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UC_RUN_C \func_name
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UC_INDEFINITE_LOOP
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.endm
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.macro UC_EXCEPTIONS_ARC7 p2p_reg
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UC_TRACE
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ld.di r0, [\p2p_reg]
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st.di r0, [\p2p_reg]
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ld.di r0, [\p2p_reg]
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sync
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rtie
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.endm
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.macro UC_EXCEPTIONS_ARC6 p2p_reg
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UC_TRACE
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ld.di r0, [\p2p_reg]
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st.di r0, [\p2p_reg]
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ld.di r0, [\p2p_reg]
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j.f [ilink1]
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.endm
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#endif
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