159 lines
4.7 KiB
C
159 lines
4.7 KiB
C
/*
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* (C) Copyright 2006
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* Mindspeed Technologies, Inc. <www.mindspeed.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/bsp.h>
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#include <asm/hardware.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if !defined(CONFIG_UART0) && !defined(CONFIG_UART1)
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#error must define one of CONFIG_UART0 or CONFIG_UART1
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#endif
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struct uart_regs {
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volatile u32 data; /* Receive/Transmit data register */
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volatile u32 ier; /* Interrupt Enable register */
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volatile u32 iir_fcr; /* Interrupt Identity register / FIFO Control register */
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volatile u32 lcr; /* Line Control register */
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volatile u32 mcr; /* Modem Control register */
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volatile u32 lsr; /* Line Status register */
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volatile u32 msr; /* Modem Status register */
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volatile u32 sr; /* Scratch register */
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};
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struct uart_dl_regs {
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volatile u32 dll; /* Divisor Latch (Low) */
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volatile u32 dlh; /* Divisor Latch (High) */
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};
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/* Interrupt Enable Register */
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/* UART 16550 */
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#define IER_RDI (1 << 0) /* Enable Received Data Available Interrupt */
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#define IER_THRI (1 << 1) /* Enable Transmitter holding register Interrupt */
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#define IER_RLSI (1 << 2) /* Enable receiver line status Interrupt */
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#define IER_MSI (1 << 3) /* Enable Modem status Interrupt */
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#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
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#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
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#define IIR_TOD (1 << 3) /* Time Out Detected */
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#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
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#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
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#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
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/* UART 16550 FIFO Control Register */
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#define FCR_FIFOEN (1 << 0)
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#define FCR_RCVRRES (1 << 1)
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#define FCR_XMITRES (1 << 2)
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#define LCR_CHAR_LEN_5 0x00 /* default */
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#define LCR_CHAR_LEN_6 0x01
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#define LCR_CHAR_LEN_7 0x02
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#define LCR_CHAR_LEN_8 0x03
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#define LCR_TWO_STOP (1 << 2) /* Two stop bit! */
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#define LCR_PEN (1 << 3) /* Parity Enable */
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#define LCR_EPS (1 << 4) /* Even Parity Select */
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#define LCR_PS (1 << 5) /* Enable Parity Stuff */
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#define LCR_SBRK (1 << 6) /* Start Break */
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#define LCR_PSB (1 << 7) /* Parity Stuff Bit */
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#define LCR_DLAB (1 << 7) /* UART 16550 Divisor Latch Assess */
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#define LSR_RXFIFO_ERROR (1 << 7) /* FIFO Error Status */
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#define LSR_TEMT (1 << 6) /* Transmitter Empty */
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#define LSR_THRE (1 << 5) /* Transmit Data Request */
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#define LSR_BI (1 << 4) /* Break Interrupt */
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#define LSR_FE (1 << 3) /* Framing Error */
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#define LSR_PE (1 << 2) /* Parity Error */
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#define LSR_OE (1 << 1) /* Overrun Error */
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#define LSR_DR (1 << 0) /* Data Ready */
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#ifdef CONFIG_UART0
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struct uart_regs *uart = (struct uart_regs *) UART0_BASEADDR;
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struct uart_dl_regs *uart_dl = (struct uart_dl_regs *) UART0_BASEADDR;
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#else
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struct uart_regs * uart = (struct uart_regs *) UART1_BASEADDR;
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struct uart_dl_regs * uart_dl = (struct uart_dl_regs *) UART1_BASEADDR;
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#endif
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void serial_setbrg (void)
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{
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int baudrate;
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unsigned int reg;
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unsigned int clk = SoC_clk_amba_get();
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if ((baudrate = gd->baudrate) <= 0)
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baudrate = CONFIG_BAUDRATE;
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reg = clk / (baudrate * 16);
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uart->lcr |= LCR_DLAB; /* Enable Divisor Latch access */
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uart_dl->dll = reg & 0xFF; /* Set Divisor Latch Low */
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uart_dl->dlh = (reg >> 8) & 0xFF; /* Set Divisor Latch high */
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uart->lcr &= ~LCR_DLAB; /* Disable Divisor Latch access */
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}
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int serial_init (void)
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{
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#ifdef CONFIG_UART1
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SoC_ioctrl_cfg(IOCTRL_UART1, 1);
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SoC_ioctrl_cfg(IOCTRL_UART0, 0);
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#endif
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uart->ier = 0x00;
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uart->iir_fcr = 0x00;
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uart->lcr = LCR_CHAR_LEN_8;
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serial_setbrg ();
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uart->data = 0;
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uart->iir_fcr = FCR_RCVRRES | FCR_XMITRES | FCR_FIFOEN;
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return (0);
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}
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void serial_putc (const char c)
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{
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/* wait for room in the tx FIFO */
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while ((uart->lsr & LSR_THRE) == 0) ;
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uart->data = c;
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if (c == '\n')
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serial_putc ('\r');
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}
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void serial_puts (const char *s)
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{
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while (*s) {
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serial_putc (*s++);
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}
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}
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int serial_getc (void)
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{
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while ((uart->lsr & LSR_DR) == 0);
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return (char)uart->data & 0xff;
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}
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int serial_tstc (void)
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{
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return uart->lsr & LSR_DR;
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}
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