180 lines
5.7 KiB
C
180 lines
5.7 KiB
C
/*
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* Copyright Codito Technologies (www.codito.com)
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*
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* include/asm-arc/arc_emac.h
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*
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* Copyright (C)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Authors : Sandeep Patil (sandeep.patil@codito.com)
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* Pradeep Sawlani(pradeep.sawlani@codito.com)
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*/
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#ifndef __ARC_EMAC_H
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#define __ARC_EMAC_H
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#include <config.h>
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/* Mtu */
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#define ETH_MTU 1500
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/* Ethernet frame length */
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#define ETH_FRAME_LEN 1514
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#define ETH_HLEN 14
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/* Timeout time for tranmission */
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#define TX_TIMEOUT (400*HZ/1000)
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/* Buffer descriptors */
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#define TX_BDT_LEN 10 /* Number of recieve BD's */
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#define RX_BDT_LEN 10 /* Number of transmit BD's */
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/* Size of RX buffers, min = 0 (pointless) max = 2048 (MAX_RX_BUFFER_LEN)
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* MAC reference manual recommends a value slightly greater than the
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* maximum size of the packet expected other wise it will chain
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* a zero size buffer desc if a packet of exactly RX_BUFFER_LEN comes.
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* VMAC will chain buffers if a packet bigger than this arrives.
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*/
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#define RX_BUFFER_LEN (ETH_FRAME_LEN + 4)
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#define MAX_RX_BUFFER_LEN 0x800 /* 2^11 = 2048 = 0x800 */
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#define MAX_TX_BUFFER_LEN 0x800 /* 2^11 = 2048 = 0x800 */
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/* 14 bytes of ethernet header, 8 bytes pad to prevent buffer chaining
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* of maximum sized ethernet packets (1514 bytes)
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*/
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#define VMAC_BUFFER_PAD ETH_HLEN + 8
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/* VMAC register definitions, offsets in the ref manual are in bytes */
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#define ID_OFFSET 0x0/0x4
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#define MDIO_DATA_OFFSET 0x34/0x4
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#define ADDRL_OFFSET 0x24/0x4
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#define ADDRH_OFFSET 0x28/0x4
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#define RXRINGPTR_OFFSET 0x20/0x4
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#define TXRINGPTR_OFFSET 0x1c/0x4
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#define POLLRATE_OFFSET 0x10/0x4
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#define ENABLE_OFFSET 0x08/0x4
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#define STAT_OFFSET 0x04/0x4
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#define CONTROL_OFFSET 0x0c/0x4
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#define LAFL_OFFSET 0x2c/0x4
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#define LAFH_OFFSET 0x30/0x4
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/* STATUS and ENABLE Register bit masks */
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#define TXINT_MASK (1<<0) /* Transmit interrupt */
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#define RXINT_MASK (1<<1) /* Recieve interrupt */
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#define ERR_MASK (1<<2) /* Error interrupt */
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#define TXCH_MASK (1<<3) /* Transmit chaining error interrupt */
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#define MSER_MASK (1<<4) /* Missed packet counter error */
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#define RXCR_MASK (1<<8) /* RXCRCERR counter rolled over */
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#define RXFR_MASK (1<<9) /* RXFRAMEERR counter rolled over */
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#define RXFL_MASK (1<<10) /* RXOFLOWERR counter rolled over */
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#define MDIO_MASK (1<<12) /* MDIO complete */
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#define TXPL_MASK (1<<31) /* TXPOLL */
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/* CONTROL Register bit masks */
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#define EN_MASK (1<<0) /* VMAC enable */
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#define TXRN_MASK (1<<3) /* TX enable */
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#define RXRN_MASK (1<<4) /* RX enable */
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#define DSBC_MASK (1<<8) /* Disable recieve broadcast */
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#define ENFL_MASK (1<<10) /* Enable Full Duplex */
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#define PROM_MASK (1<<11) /* Promiscuous mode */
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/* Buffer descriptor INFO bit masks */
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#define OWN_MASK (1<<31) /* 0-CPU owns buffer, 1-VMAC owns buffer */
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#define FRST_MASK (1<<16) /* First buffer in chain */
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#define LAST_MASK (1<<17) /* Last buffer in chain */
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#define LEN_MASK 0x000007FF /* last 11 bits */
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/* ARCangel board PHY Identifier */
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#define PHY_ID 0x3
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/* LXT970 register definitions */
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#define LXT970A_CTRL_REG 0x00
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#define LXT970A_STATUS_REG 0x01
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#define LXT970A_AUTONEG_ADV_REG 0x04
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#define LXT970A_AUTONEG_LINK_REG 0x05
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#define LXT970A_MIRROR_REG 0x10
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#define LXT970A_STATUS2_REG 0x11
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/* LXT970A control register bit definitions */
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#define LXT970A_CTRL_RESET 0x8000
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#define LXT970A_CTRL_LOOPBACK 0x4000
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#define LXT970A_CTRL_SPEED 0x2000
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#define LXT970A_CTRL_AUTONEG 0x1000
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#define LXT970A_CTRL_DUPLEX 0x0100
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#define LXT970A_CTRL_RESTART_AUTO 0x0200
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#define LXT970A_CTRL_COLL 0x0080
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#define LXT970A_CTRL_DUPLEX_MODE 0x0100
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/* Auto-negatiation advertisement register bit definitions */
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#define LXT970A_AUTONEG_ADV_100BTX_FULL 0x100
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#define LXT970A_AUTONEG_ADV_100BTX 0x80
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#define LXT970A_AUTONEG_ADV_10BTX_FULL 0x40
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#define LXT970A_AUTONEG_ADV_10BT 0x20
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#define AUTONEG_ADV_IEEE_8023 0x1
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/* Auto-negatiation Link register bit definitions */
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#define LXT970A_AUTONEG_LINK_100BTX_FULL 0x100
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#define LXT970A_AUTONEG_LINK_100BTX 0x80
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#define LXT970A_AUTONEG_LINK_10BTX_FULL 0x40
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/* Status register bit definitions */
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#define LXT970A_STATUS_COMPLETE 0x20
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#define LXT970A_STATUS_AUTONEG_ABLE 0x04
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#define LXT970A_STATUS2_COMPLETE 0x80
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/* Status2 register bit definitions */
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#define LXT970A_STATUS2_POLARITY 0x20
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#define LXT970A_STATUS2_FULL 0x200
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#define LXT970A_STATUS2_LINK_UP 0x400
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#define LXT970A_STATUS2_100 0x4000
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//#define ARCTANGENT_EMAC_SETUP
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//#define ARCTANGENT_EMAC_DEBUG
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#define __mdio_write(stat_reg,mdio_data_reg, phy_id, phy_reg, val) do { \
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*(mdio_data_reg) = (0x50020000 | phy_id << 23 | \
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phy_reg << 18 | (val & 0xffff)) ; \
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while (!(*(stat_reg) & MDIO_MASK)); \
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*stat_reg = MDIO_MASK;\
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}while(0)
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#define __mdio_read(stat_reg, mdio_data_reg, phy_id, phy_reg, val) do { \
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*(mdio_data_reg) = (0x60020000 | phy_id << 23 | phy_reg << 18 );\
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while (! ((*stat_reg) & MDIO_MASK) );\
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*stat_reg = MDIO_MASK; \
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val = *(mdio_data_reg) & 0xffff; \
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}while(0)
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#define arc_read_uncached_32(ptr) \
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({ \
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unsigned int __ret; \
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__asm__ __volatile__ ("ld.di %0, [%1]":"=r"(__ret):"r"(ptr)); \
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__ret; \
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})
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#define arc_write_uncached_32(ptr, data) \
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({ \
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__asm__ __volatile__ ("st.di %0, [%1]"::"r"(data), "r"(ptr)); \
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})
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struct aa3_buffer_desc {
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unsigned int info;
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void *data;
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};
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#endif /* __ARC_EMAC_H */
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