90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
/*
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* (C) Copyright 2006
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* Mindspeed Technologies, Inc. <www.mindspeed.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef _IDMA_H
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#define _IDMA_H
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#define HDMA_SOFT_RESET (IDMA_BASEADDR + 0x0000)
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#define IDMA_EMAC0_BASEADDR (IDMA_BASEADDR + 0x0100)
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#define MMPU_START (IDMA_BASEADDR + 0x0200)
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#define MMPU_HEAD (IDMA_BASEADDR + 0x0204)
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#define MMPU_BURST (IDMA_BASEADDR + 0x0208)
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#define MMPU_SOFT_RESET (IDMA_BASEADDR + 0x0220)
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#define PUMM_START (IDMA_BASEADDR + 0x0280)
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#define PUMM_HEAD (IDMA_BASEADDR + 0x0284)
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#define PUMM_BURST (IDMA_BASEADDR + 0x0288)
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#define PUMM_SOFT_RESET (IDMA_BASEADDR + 0x02A0)
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#define MMFIFO_START (IDMA_BASEADDR + 0x0300)
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#define MMFIFO_HEAD (IDMA_BASEADDR + 0x0304)
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#define MMFIFO_BURST (IDMA_BASEADDR + 0x0308)
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#define MMFIFO_SOFT_RESET (IDMA_BASEADDR + 0x0320)
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#define FIFOMM_START (IDMA_BASEADDR + 0x0380)
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#define FIFOMM_HEAD (IDMA_BASEADDR + 0x0384)
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#define FIFOMM_BURST (IDMA_BASEADDR + 0x0388)
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#define FIFOMM_SOFT_RESET (IDMA_BASEADDR + 0x03A0)
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#define IDMA_EMAC1_BASEADDR (IDMA_BASEADDR + 0x0700)
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/* Memory to EMAC register offsets */
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#define MMEM_START 0x00
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#define MMEM_HEAD 0x04
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#define MMEM_BURST 0x08
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#define MMEM_SOFT_RESET 0x20
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/* EMAC to Memory register offsets */
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#define EMMM_START 0x80
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#define EMMM_HEAD 0x84
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#define EMMM_BURST 0x88
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#define EMMM_SOFT_RESET 0xA0
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#define FDESC_ALIGN_BYTES 0x10
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//************ IDMA registers and masks *****************
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#define IDMA_FSTATUS_FRAME_DONE_MASK 0x80000000
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#define IDMA_FSTATUS_STATUS_MASK 0x03FFFFFF
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#define IDMA_FCONTROL_PHY_NB_MASK 0x00000070
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#define IDMA_FCONTROL_PHY_OFFSET 0x00000004
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#define IDMA_FCONTROL_IRQEN 0x00000004
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#define IDMA_FCONTROL_FLAST 0x00000002
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#define IDMA_FCONTROL_FREADY 0x00000001
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#define IDMA_BCONTROL_BLAST 0x00010000
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#define IDMA_BCONTROL_BLEN_MASK 0x0000FFFF
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#define IDMA_FSTATUS_FDONE 0x80000000
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#define IDMA_FSTATUS_BIT27 0x08000000
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#define IDMA_FSTATUS_FKEEP 0x04000000
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#define IDMA_START 0x00000001
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#define IDMA_BURST_MASK 0x000000FF
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#define IDMA_PRTY_MASK 0x00000700
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#endif
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