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12 Commits
stm_debug
...
9f1e7ba267
| Author | SHA1 | Date | |
|---|---|---|---|
| 9f1e7ba267 | |||
| 9086bf3efb | |||
| 3bf5a8cc19 | |||
| b9c371ed58 | |||
| 9d96b3d4f2 | |||
| bb70e0675a | |||
| 11e50b05e4 | |||
| e951eaef7c | |||
| ce25cba61b | |||
| 691d5dc1ea | |||
| 052d3fc5c0 | |||
| 4967cd9b32 |
@@ -56,6 +56,7 @@ void SDIO_IRQHandler(void);
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void TIM6_DAC_IRQHandler(void);
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void DMA2_Stream3_IRQHandler(void);
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void DMA2_Stream6_IRQHandler(void);
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void DMA2_Stream7_IRQHandler(void);
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/* USER CODE BEGIN EFP */
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/* USER CODE END EFP */
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+7
-4
@@ -51,11 +51,9 @@ void CAN_Logger_Init(CAN_HandleTypeDef *hcan1, CAN_HandleTypeDef *hcan2)
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filter.FilterBank = 0;
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if (HAL_CAN_ConfigFilter(hcan1, &filter) != HAL_OK) Error_Handler();
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if (HAL_CAN_Start(hcan1) != HAL_OK) Error_Handler();
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filter.FilterBank = 14;
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if (HAL_CAN_ConfigFilter(hcan2, &filter) != HAL_OK) Error_Handler();
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if (HAL_CAN_Start(hcan2) != HAL_OK) Error_Handler();
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}
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/* END CAN_Logger_Init */
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@@ -77,7 +75,8 @@ void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)
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// TODO: manage the case of FIFO overflow
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if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &rxHeader, data) != HAL_OK) return;
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message.id = rxHeader.ExtId;
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if (rxHeader.IDE == CAN_ID_EXT) message.id = rxHeader.ExtId;
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else message.id = rxHeader.StdId;
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message.dlc = rxHeader.DLC;
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message.isExtended = (rxHeader.IDE == CAN_ID_EXT);
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message.source = (hcan->Instance == CAN1) ? 1 : 2;
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@@ -113,15 +112,19 @@ void vCANListener(void *argument)
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osMessageQueueId_t queue = (hcan->Instance == CAN1) ? xCAN1RxQueue : xCAN2RxQueue;
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CanMessage_t message;
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if (HAL_CAN_Start(hcan) != HAL_OK) Error_Handler();
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HAL_CAN_ActivateNotification(hcan, CAN_IT_RX_FIFO0_MSG_PENDING);
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uint32_t irqn = (hcan->Instance == CAN1) ? CAN1_RX0_IRQn : CAN2_RX0_IRQn;
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HAL_NVIC_SetPriority(irqn, 6, 0);
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HAL_NVIC_EnableIRQ(irqn);
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for (;;)
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{
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if (osMessageQueueGet(queue, &message, NULL, osWaitForever) == osOK)
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{
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// J1939 decoding
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// RELAY: Push to the UART queue
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osMessageQueuePut(xUARTQueue, &message, 0U, 0U);
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}
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}
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+17
-10
@@ -101,20 +101,27 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
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*/
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void vUARTLogger(void *argument)
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{
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CanMessage_t message;
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char tx_buffer[45];
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CanMessage_t message;
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char tx_buffer[45];
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for (;;)
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for (;;)
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{
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DEBUG_PRINT("Waiting for CAN traffic...\r\n");
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if (osMessageQueueGet(xUARTQueue, &message, NULL, osWaitForever) == osOK)
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{
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DEBUG_PRINT("Waiting for CAN traffic...\r\n");
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if (osMessageQueueGet(xUARTQueue, &message, NULL, osWaitForever) == osOK)
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osSemaphoreAcquire(xUARTDMASemaphore, osWaitForever);
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int len = format_can_message(tx_buffer, message.source, &message);
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if (HAL_UART_Transmit_DMA(&huart1, (uint8_t*)tx_buffer, len) == HAL_OK)
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{
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DEBUG_PRINT("CAN frame detected\r\n");
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int len = format_can_message(tx_buffer, message.source, &message);
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HAL_UART_Transmit_DMA(&huart1, (uint8_t*)tx_buffer, len);
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osSemaphoreAcquire(xUARTDMASemaphore, osWaitForever);
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DEBUG_PRINT("CAN frame sent via UART\r\n");
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DEBUG_PRINT("CAN frame sent via UART\r\n");
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}
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else
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{
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osSemaphoreRelease(xUARTDMASemaphore);
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DEBUG_PRINT("HAL error, CAN frame NOT sent!\r\n");
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}
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}
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}
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}
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/* END vUARTLoggerListen */
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+20
-13
@@ -46,6 +46,7 @@ DMA_HandleTypeDef hdma_sdio_rx;
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DMA_HandleTypeDef hdma_sdio_tx;
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UART_HandleTypeDef huart1;
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DMA_HandleTypeDef hdma_usart1_tx;
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/* USER CODE BEGIN PV */
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LED_Config led_can1 = {GPIOB, GPIO_PIN_5};
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@@ -76,11 +77,10 @@ static void MX_SDIO_SD_Init(void);
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static void MX_USART1_UART_Init(void);
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/* USER CODE BEGIN PFP */
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int _write(int file, char *ptr, int len) {
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for (int i = 0; i < len; i++) {
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ITM_SendChar((*ptr++));
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}
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return len;
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int _write(int file, char *ptr, int len)
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{
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for (int i = 0; i < len; i++) ITM_SendChar((*ptr++));
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return len;
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}
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/* USER CODE END PFP */
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@@ -97,10 +97,14 @@ int main(void)
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{
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/* USER CODE BEGIN 1 */
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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ITM->LAR = 0xC5ACCE55;
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ITM->TER = 1 << 0;
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ITM->TCR = ITM_TCR_ITMENA_Msk | ITM_TCR_SYNCENA_Msk | ITM_TCR_SWOENA_Msk;
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if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk)
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{
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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ITM->LAR = 0xC5ACCE55;
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ITM->TER = 1 << 0;
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ITM->TCR = ITM_TCR_ITMENA_Msk | ITM_TCR_SYNCENA_Msk | ITM_TCR_SWOENA_Msk;
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}
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DEBUG_PRINT("Booting system\r\n");
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/* USER CODE END 1 */
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@@ -170,7 +174,7 @@ int main(void)
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/* USER CODE END RTOS_MUTEX */
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/* USER CODE BEGIN RTOS_SEMAPHORES */
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xUARTDMASemaphore = osSemaphoreNew(1, 0, NULL);
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xUARTDMASemaphore = osSemaphoreNew(1, 1, NULL);
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if (xUARTDMASemaphore == NULL) Error_Handler();
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/* USER CODE END RTOS_SEMAPHORES */
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@@ -276,7 +280,7 @@ static void MX_CAN1_Init(void)
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/* USER CODE END CAN1_Init 1 */
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hcan1.Instance = CAN1;
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hcan1.Init.Prescaler = 4;
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hcan1.Init.Prescaler = 8;
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hcan1.Init.Mode = CAN_MODE_SILENT;
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hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ;
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hcan1.Init.TimeSeg1 = CAN_BS1_16TQ;
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@@ -313,7 +317,7 @@ static void MX_CAN2_Init(void)
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/* USER CODE END CAN2_Init 1 */
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hcan2.Instance = CAN2;
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hcan2.Init.Prescaler = 8;
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hcan2.Init.Prescaler = 16;
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hcan2.Init.Mode = CAN_MODE_SILENT;
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hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ;
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hcan2.Init.TimeSeg1 = CAN_BS1_16TQ;
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@@ -386,7 +390,7 @@ static void MX_USART1_UART_Init(void)
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/* USER CODE END USART1_Init 1 */
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huart1.Instance = USART1;
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huart1.Init.BaudRate = 1152000;
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huart1.Init.BaudRate = 115200;
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huart1.Init.WordLength = UART_WORDLENGTH_8B;
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huart1.Init.StopBits = UART_STOPBITS_1;
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huart1.Init.Parity = UART_PARITY_NONE;
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@@ -419,6 +423,9 @@ static void MX_DMA_Init(void)
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/* DMA2_Stream6_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn);
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/* DMA2_Stream7_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
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/* USER CODE BEGIN MX_DMA_Init 1 */
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DEBUG_PRINT("DMA initialized!\r\n");
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@@ -26,6 +26,8 @@ extern DMA_HandleTypeDef hdma_sdio_rx;
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extern DMA_HandleTypeDef hdma_sdio_tx;
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extern DMA_HandleTypeDef hdma_usart1_tx;
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/* Private typedef -----------------------------------------------------------*/
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/* USER CODE BEGIN TD */
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@@ -371,6 +373,25 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
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GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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/* USART1 DMA Init */
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/* USART1_TX Init */
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hdma_usart1_tx.Instance = DMA2_Stream7;
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hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4;
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hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
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hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
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hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
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hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
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hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
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hdma_usart1_tx.Init.Mode = DMA_NORMAL;
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hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
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hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
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if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
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{
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Error_Handler();
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}
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__HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
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/* USER CODE BEGIN USART1_MspInit 1 */
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/* USER CODE END USART1_MspInit 1 */
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@@ -401,6 +422,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
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*/
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HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
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/* USART1 DMA DeInit */
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HAL_DMA_DeInit(huart->hdmatx);
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/* USER CODE BEGIN USART1_MspDeInit 1 */
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/* USER CODE END USART1_MspDeInit 1 */
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@@ -58,6 +58,7 @@
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extern DMA_HandleTypeDef hdma_sdio_rx;
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extern DMA_HandleTypeDef hdma_sdio_tx;
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extern SD_HandleTypeDef hsd;
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extern DMA_HandleTypeDef hdma_usart1_tx;
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extern TIM_HandleTypeDef htim6;
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/* USER CODE BEGIN EV */
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@@ -218,6 +219,20 @@ void DMA2_Stream6_IRQHandler(void)
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/* USER CODE END DMA2_Stream6_IRQn 1 */
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}
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/**
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* @brief This function handles DMA2 stream7 global interrupt.
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*/
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void DMA2_Stream7_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Stream7_IRQn 0 */
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/* USER CODE END DMA2_Stream7_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_usart1_tx);
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/* USER CODE BEGIN DMA2_Stream7_IRQn 1 */
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/* USER CODE END DMA2_Stream7_IRQn 1 */
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}
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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+13
-1
@@ -20,7 +20,8 @@ CAN2.Mode=CAN_MODE_SILENT
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CAN2.Prescaler=8
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Dma.Request0=SDIO_RX
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Dma.Request1=SDIO_TX
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Dma.RequestsNb=2
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Dma.Request2=USART1_TX
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Dma.RequestsNb=3
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Dma.SDIO_RX.0.Direction=DMA_PERIPH_TO_MEMORY
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Dma.SDIO_RX.0.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SDIO_RX.0.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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@@ -47,6 +48,16 @@ Dma.SDIO_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_WORD
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Dma.SDIO_TX.1.PeriphInc=DMA_PINC_DISABLE
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Dma.SDIO_TX.1.Priority=DMA_PRIORITY_LOW
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Dma.SDIO_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.USART1_TX.2.Direction=DMA_MEMORY_TO_PERIPH
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Dma.USART1_TX.2.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.USART1_TX.2.Instance=DMA2_Stream7
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Dma.USART1_TX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.USART1_TX.2.MemInc=DMA_MINC_ENABLE
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Dma.USART1_TX.2.Mode=DMA_NORMAL
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Dma.USART1_TX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.USART1_TX.2.PeriphInc=DMA_PINC_DISABLE
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Dma.USART1_TX.2.Priority=DMA_PRIORITY_LOW
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Dma.USART1_TX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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FREERTOS.FootprintOK=true
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FREERTOS.IPParameters=Tasks01,configUSE_NEWLIB_REENTRANT,FootprintOK
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FREERTOS.Tasks01=DefaultTask,49,128,can_listen,Default,NULL,Dynamic,NULL,NULL
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@@ -96,6 +107,7 @@ MxDb.Version=DB.6.0.170
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NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
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NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
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NVIC.DMA2_Stream6_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
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NVIC.DMA2_Stream7_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
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NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
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NVIC.ForceEnableDMAVector=true
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NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
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