WIP: Isolate CAN FreeRTOS stacks and queues in CCMRAM to eliminate future DMA bus contention #19

2026-06-16T01:38:56+02:00

eeeck commented

2026-06-16 01:38:56 +02:00

This change isolates the real-time CAN ISR and context switches from the main AHB bus to the dedicated Core Coupled memory bus.

Advantage: zero-wait-state execution even when high-bandwidth DMA peripherals (like SDIO or UART) are actively transferring data.
Disadvantage: while code is not complex, it is maybe overengineering... but we have CCRAM why not use it for the core job lol

This change isolates the real-time CAN ISR and context switches from the main AHB bus to the dedicated Core Coupled memory bus. Advantage: zero-wait-state execution even when high-bandwidth DMA peripherals (like SDIO or UART) are actively transferring data. Disadvantage: while code is not complex, it is maybe overengineering... but we have CCRAM why not use it for the core job lol

eeeck added the enhancement experimental labels 2026-06-16 01:38:56 +02:00

eeeck self-assigned this 2026-06-16 01:38:56 +02:00

eeeck added this to the Thesis SCRUM project 2026-06-16 01:38:56 +02:00

eeeck added 7 commits 2026-06-16 01:38:57 +02:00

eeeck moved this to In Progress in Thesis SCRUM on 2026-06-16 01:39:28 +02:00

eeeck added a new dependency 2026-06-16 01:39:49 +02:00

#9 Place Time-Critical Data in CCMRAM

eeeck moved this to Paused in Thesis SCRUM on 2026-06-16 19:12:49 +02:00

This pull request has changes conflicting with the target branch.

Core/Src/main.c

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#9 Place Time-Critical Data in CCMRAM

eeeck/CANdigger

Reference: eeeck/CANdigger#19