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gates dump

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This commit is contained in:
Erick
2022-03-01 23:35:17 +01:00
parent 540aac9fca
commit 0646b73f9a
24 changed files with 455 additions and 2 deletions
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README.md
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@@ -7,4 +7,5 @@ Square One is a virtual computer built from scratch, starting from the logic gat
The gates are designed following a behavioural modelling philosophy (mostly for learning purposes, even though a data flow modelling system would be preferible for big projects)
## Resources
- Online Verilog Compiler: https://www.tutorialspoint.com/compile_verilog_online.php
- Online Verilog Compiler: https://www.tutorialspoint.com/compile_verilog_online.php
- Online FPGA Simulator: https://simulator.nirajmmenon.com/
gates/and16.v
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module and16(y16, a16, b16);
input [15:0] a16;
input [15:0] b16;
output [15:0] y16;
and(y16[0], a16[0], b16[0]);
and(y16[1], a16[1], b16[1]);
and(y16[2], a16[2], b16[2]);
and(y16[3], a16[3], b16[3]);
and(y16[4], a16[4], b16[4]);
and(y16[5], a16[5], b16[5]);
and(y16[6], a16[6], b16[6]);
and(y16[7], a16[7], b16[7]);
and(y16[8], a16[8], b16[8]);
and(y16[9], a16[9], b16[9]);
and(y16[10], a16[10], b16[10]);
and(y16[11], a16[11], b16[11]);
and(y16[12], a16[12], b16[12]);
and(y16[13], a16[13], b16[13]);
and(y16[14], a16[14], b16[14]);
and(y16[15], a16[15], b16[15]);
endmodule
gates/and8way.v
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module and8way(out, i0, i1, i2, i3, i4, i5, i6, i7);
input i0, i1, i2, i3, i4, i5, i6, i7;
output out;
wire tmp01, tmp23, tmp45, tmp67, tmp0123, tmp4567;
and(tmp01, i0, i1);
and(tmp23, i2, i3);
and(tmp45, i4, i5);
and(tmp67, i6, i17);
and(tmp0123, tmp01, tmp23);
and(tmp4567, tmp45, tmp67);
and(out, tmp0123, tmp4567);
endmodule
gates/and8way16.v
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include "and16.v"
module and8way16(out, i0, i1, i2, i3, i4, i5, i6, i7);
input [15:0]i0;
input [15:0]i1;
input [15:0]i2;
input [15:0]i3;
input [15:0]i4;
input [15:0]i5;
input [15:0]i6;
input [15:0]i7;
output [15:0] out;
wire [15:0]tmp01;
wire [15:0]tmp23;
wire [15:0]tmp45;
wire [15:0]tmp67;
wire [15:0]tmp0123;
wire [15:0]tmp4567;
and16 and01(tmp01, i0, i1);
and16 and23(tmp23, i2, i3);
and16 and45(tmp45, i4, i5);
and16 and67(tmp67, i6, i7);
and16 and0123(tmp0123, tmp01, tmp23);
and16 and4567(tmp4567, tmp45, tmp67);
and16 final(out, tmp0123, tmp4567);
endmodule
gates/demux16.v
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module demux16(y16, z16, a16, sel);
input [15:0] a16;
input [15:0] z16;
input [1:0] sel;
output [15:0] y16;
demux(y16[0], z16[0], a16[0], sel);
demux(y16[1], z16[1], a16[1], sel);
demux(y16[2], z16[2], a16[2], sel);
demux(y16[3], z16[3], a16[3], sel);
demux(y16[4], za16[4], a16[4], sel);
demux(y16[5], z16[5], a16[5], sel);
demux(y16[6], z16[6], a16[6], sel);
demux(y16[7], z16[7], a16[7], sel);
demux(y16[8], z16[8], a16[8], sel);
demux(y16[9], z16[9], a16[9], sel);
demux(y16[10], z16[10], a16[10], sel);
demux(y16[11], z16[11], a16[11], sel);
demux(y16[12], z16[12], a16[12], sel);
demux(y16[13], z16[13], a16[13], sel);
demux(y16[14], z16[14], a16[14], sel);
demux(y16[15], z16[15], a16[15], sel);
endmodule
gates/demux4way.v
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include "demux.v";
module demux4way(out0, out1, out2, out3, i0, i1, sel);
input i0, i1;
input [3:0] sel;
output out0, out1, out2, out3;
wire [3:0] [1:0] sel0 = sel;
wire [0:3] [1:0] sel1 = sel;
demux(out0, out1, i0, sel0);
demux(out2, out3, i1, sel1);
endmodule
gates/demux4way16.v
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include "demux.v";
module demux4way(out0, out1, out2, out3, i0, i1, sel);
input [15:0]i0;
input [15:0]i1;
input [3:0]sel;
output [15:0]out0;
output [15:0]out1;
output [15:0]out2;
output [15:0]out3;
wire [3:0] [1:0] sel0 = sel;
wire [0:3] [1:0] sel1 = sel;
not(notSel0, sel0);
not(notSel1, sel1);
and(out1, i0, sel0);
and(out0, i0, notSel0);
and(out2, i1, sel1);
and(out3, i1, notSel1);
endmodule
gates/demux8way.v
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include "demux4way.v";
module demux8way(out0, out1, out3, out4, out5, out6, out7, i0, i1, i2, i3, sel);
input i0, i1, i2, i3;
input [7:0]sel;
output out0,
wire [7:0] [3:0] sel0 = sel;
wire [0:7] [3:0] sel1 = sel;
demux4way(out0 ,out1, out2, out3, i0, i1, sel0);
demux4way(out4, out5, out6, out7, i2, i3, sel1);
endmodule
gates/demux8way16.v
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include "demux4way16.v";
module demux8way(out0, out1, out3, out4, out5, out6, out7, i0, i1, i2, i3, sel);
input [15:0]i0;
input [15:0]i1;
input [15:0]i2;
input [15:0]i3;
input [7:0]sel;
output [15:0]out0;
output [15:0]out1;
output [15:0]out2;
output [15:0]out3;
output [15:0]out4;
output [15:0]out5;
output [15:0]out6;
output [15:0]out7;
wire [7:0] [3:0] sel0 = sel;
wire [0:7] [3:0] sel1 = sel;
demux4way16(out0 ,out1, out2, out3, i0, i1, sel0);
demux4way16(out4, out5, out6, out7, i2, i3, sel1);
endmodule
gates/mux.v
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@@ -1,6 +1,6 @@
module mux(y, a, b, sel);
input a, b, sel;
inout y;
output y;
wire notSel, andA, andB;
not(notSel, sel);
gates/mux16.v
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module mux16(y16, a16, b16, sel);
input [15:0] a16;
input[15:0] b16;
input [1:0]sel;
output [15:0] y16;
mux(y16[0], a16[0], b16[0], sel);
mux(y16[1], a16[1], b16[1], sel);
mux(y16[2], a16[2], b16[2], sel);
mux(y16[3], a16[3], b16[3], sel);
mux(y16[4], a16[4], b16[4], sel);
mux(y16[5], a16[5], b16[5], sel);
mux(y16[6], a16[6], b16[6], sel);
mux(y16[7], a16[7], b16[7], sel);
mux(y16[8], a16[8], b16[8], sel);
mux(y16[9], a16[9], b16[9], sel);
mux(y16[10], a16[10], b16[10], sel);
mux(y16[11], a16[11], b16[11], sel);
mux(y16[12], a16[12], b16[12], sel);
mux(y16[13], a16[13], b16[13], sel);
mux(y16[14], a16[14], b16[14], sel);
mux(y16[15], a16[15], b16[15], sel);
endmodule
gates/mux4way.v
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include "mux.v";
include "or4way.v";
module mux4way(out, i0, i1, i2, i3, sel0, sel1);
input i0, i1, i2, i3;
input [2:0]sel;
output [3:0]out;
wire tmp0, tmp1, tmp2, tmp3;
not(notSel, sel);
and(tmp0, i0, notSel);
and(tmp1, i1, sel);
and(tmp2, i2, notSel);
and(tmp3, i3, sel);
or4way(out, tmp0, tmp1, tmp2, tmp3);
endmodule
gates/mux4way16.v
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include "and16.v"
include "not16.v"
include "or4way.v"
module mux4way16(out, i0, i1, i2, i3, sel);
input [15:0]i0;
input [15:0]i1;
input [15:0]i2;
input [15:0]i3;
input [2:0]sel;
output [15:0]out;
wire [15:0]tmp0;
wire [15:0]tmp1;
wire [15:0]tmp2;
wire [15:0]tmp3;
wire [2:0] [15:0] sel16 = sel;
not16(notSel16, sel16);
and16(tmp0, i0, notSel16);
and16(tmp1, i1, sel16);
and16(tmp2, i2, notSel16);
and16(tmp3, i3, sel16);
or4way16(out, tmp0, tmp1, tmp2, tmp3);
endmodule
gates/mux8way16.v
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include "mux4way16.v";
include "mux16.v";
module mux8way16(out, i0, i1, i2, i3, i4, i5, i6, i7, sel);
input [15:0]i0;
input [15:0]i1;
input [15:0]i2;
input [15:0]i3;
input [15:0]i4;
input [15:0]i5;
input [15:0]i6;
input [15:0]i7;
input [3:0]sel;
output [15:0]out;
wire tmpMux1, tmpMux1;
wire [3:0] [1:0] sel0 = sel;
wire [0:3] [1:0] sel1 = sel;
mux4way16(tmpMux0, i0, i1, i2, i3, sel0);
mux4way16(tmpMux1, i4, i5, i6, i7, sel1);
mux16(out, tmpMux0, tmpMux1, sel);
endmodule
gates/nand16.v
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module band16(y16, a16, b16);
input [15:0]a16;
input[15:0]b16;
output [15:0]y16;
nand(y16[0], a16[0], b16[0]);
nand(y16[1], a16[1], b16[1]);
nand(y16[2], a16[2], b16[2]);
nand(y16[3], a16[3], b16[3]);
nand(y16[4], a16[4], b16[4]);
nand(y16[5], a16[5], b16[5]);
nand(y16[6], a16[6], b16[6]);
nand(y16[7], a16[7], b16[7]);
nand(y16[8], a16[8], b16[8]);
nand(y16[9], a16[9], b16[9]);
nand(y16[10], a16[10], b16[10]);
nand(y16[11], a16[11], b16[11]);
nand(y16[12], a16[12], b16[12]);
nand(y16[13], a16[13], b16[13]);
nand(y16[14], a16[14], b16[14]);
nand(y16[15], a16[15], b16[15]);
endmodule
gates/nor16.v
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module xnor16(y16, a16, b16);
input [15:0] a16;
input [15:0] b16;
output [15:0] y16;
xnor(y16[0], a16[0], b16[0]);
xnor(y16[1], a16[1], b16[1]);
xnor(y16[2], a16[2], b16[2]);
xnor(y16[3], a16[3], b16[3]);
xnor(y16[4], a16[4], b16[4]);
xnor(y16[5], a16[5], b16[5]);
xnor(y16[6], a16[6], b16[6]);
xnor(y16[7], a16[7], b16[7]);
xnor(y16[8], a16[8], b16[8]);
xnor(y16[9], a16[9], b16[9]);
xnor(y16[10], a16[10], b16[10]);
xnor(y16[11], a16[11], b16[11]);
xnor(y16[12], a16[12], b16[12]);
xnor(y16[13], a16[13], b16[13]);
xnor(y16[14], a16[14], b16[14]);
xnor(y16[15], a16[15], b16[15]);
endmodule
gates/not16.v
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module not16(y16, a16);
input [15:0] a16;
output [15:0] y16;
not(y16[0], a16[0]);
not(y16[1], a16[1]);
not(y16[2], a16[2]);
not(y16[3], a16[3]);
not(y16[4], a16[4]);
not(y16[5], a16[5]);
not(y16[6], a16[6]);
not(y16[7], a16[7]);
not(y16[8], a16[8]);
not(y16[9], a16[9]);
not(y16[10], a16[10]);
not(y16[11], a16[11]);
not(y16[12], a16[12]);
not(y16[13], a16[13]);
not(y16[14], a16[14]);
not(y16[15], a16[15]);
endmodule
gates/or16.v
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module or16(y16, a16, b16);
input [15:0] a16;
input [15:0] b16;
output [15:0] y16;
or(y16[0], a16[0], b16[0]);
or(y16[1], a16[1], b16[1]);
or(y16[2], a16[2], b16[2]);
or(y16[3], a16[3], b16[3]);
or(y16[4], a16[4], b16[4]);
or(y16[5], a16[5], b16[5]);
or(y16[6], a16[6], b16[6]);
or(y16[7], a16[7], b16[7]);
or(y16[8], a16[8], b16[8]);
or(y16[9], a16[9], b16[9]);
or(y16[10], a16[10], b16[10]);
or(y16[11], a16[11], b16[11]);
or(y16[12], a16[12], b16[12]);
or(y16[13], a16[13], b16[13]);
or(y16[14], a16[14], b16[14]);
or(y16[15], a16[15], b16[15]);
endmodule
gates/or4way.v
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module or4way(out, i0, i1, i2, i3);
input i0, i1, i2, i3;
output [3:0]out;
wire tmp01, tmp23,;
or(tmp01, i0, i1);
or(tmp23, i2, i3);
or(out, tmp01, tmp23);
endmodule
gates/or4way16.v
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module or4way16(out, i0, i1, i2, i3);
input [15:0]i0;
input [15:0]i1;
input [15:0]i2;
input [15:0]i3;
output [15:0]out;
wire [15:0]tmp01;
wire [15:0]tmp23,;
or(tmp01, i0, i1);
or(tmp23, i2, i3);
or(out, tmp01, tmp23);
endmodule
gates/or8way.v
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include "or4way.v";
module or8way(out4, i0, i1, i2, i3, i4, i5, i6, i7);
input i0, i1, i2, i3, i4, i5, i6, i7;
output out;
wire tmp0, tmp1;
or4way(tmp0, i0, i1, i2, i3);
or4way(tmp1, i4, i5, i6, i7);
or(out, tmp0, tmp1);
endmodule
gates/or8way16.v
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include "or16.v"
module or8way16(out, i0, i1, i2, i3, i4, i5, i6, i7);
input [15:0]i0;
input [15:0]i1;
input [15:0]i2;
input [15:0]i3;
input [15:0]i4;
input [15:0]i5;
input [15:0]i6;
input [15:0]i7;
output [15:0] out;
wire [15:0]tmp01;
wire [15:0]tmp23;
wire [15:0]tmp45;
wire [15:0]tmp67;
wire [15:0]tmp0123;
wire [15:0]tmp4567;
or16 or01(tmp01, i0, i1);
or16 or23(tmp23, i2, i3);
or16 or45(tmp45, i4, i5);
or16 or67(tmp67, i6, i7);
or16 or0123(tmp0123, tmp01, tmp23);
or16 or4567(tmp4567, tmp45, tmp67);
or16 final(out, tmp0123, tmp4567);
endmodule
gates/xnor16.v
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`default_nettype none
module or16(y16, a16, b16);
input [15:0] a16;
input [15:0] b16;
output [15:0] y16;
or(y16[0], a16[0], b16[0]);
or(y16[1], a16[1], b16[1]);
or(y16[2], a16[2], b16[2]);
or(y16[3], a16[3], b16[3]);
or(y16[4], a16[4], b16[4]);
or(y16[5], a16[5], b16[5]);
or(y16[6], a16[6], b16[6]);
or(y16[7], a16[7], b16[7]);
or(y16[8], a16[8], b16[8]);
or(y16[9], a16[9], b16[9]);
or(y16[10], a16[10], b16[10]);
or(y16[11], a16[11], b16[11]);
or(y16[12], a16[12], b16[12]);
or(y16[13], a16[13], b16[13]);
or(y16[14], a16[14], b16[14]);
or(y16[15], a16[15], b16[15]);
endmodule
gates/xor16.v
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`default_nettype none
module xor16(y16, a16, b16);
input [15:0] a16;
input [15:0] b16;
output [15:0] y16;
xor(y16[0], a16[0], b16[0]);
xor(y16[1], a16[1], b16[1]);
xor(y16[2], a16[2], b16[2]);
xor(y16[3], a16[3], b16[3]);
xor(y16[4], a16[4], b16[4]);
xor(y16[5], a16[5], b16[5]);
xor(y16[6], a16[6], b16[6]);
xor(y16[7], a16[7], b16[7]);
xor(y16[8], a16[8], b16[8]);
xor(y16[9], a16[9], b16[9]);
xor(y16[10], a16[10], b16[10]);
xor(y16[11], a16[11], b16[11]);
xor(y16[12], a16[12], b16[12]);
xor(y16[13], a16[13], b16[13]);
xor(y16[14], a16[14], b16[14]);
xor(y16[15], a16[15], b16[15]);
endmodule