gates dump

2022-03-01 23:35:17 +01:00
parent 540aac9fca
commit 0646b73f9a
24 changed files with 455 additions and 2 deletions
@@ -1,6 +1,6 @@
 module mux(y, a, b, sel);
    input a, b, sel;
-    inout y;
+    output y;
    wire notSel, andA, andB;

    not(notSel, sel);