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Update and16_tb.v

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Erick
2022-03-07 02:16:45 +01:00
parent e8be158685
commit 1dd49c3f40
1 changed files with 11 additions and 4 deletions
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testbench/and16_tb.v
+11 -4
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@@ -1,11 +1,18 @@
'include "predefined/and16.v" 'include "predefined/and16.v"
module and_tb(); module and16_tb();
reg [15:0]ta, [15:0]tb; reg [15:0]ta;
reg [15:0]tb;
wire [15:0]y; wire [15:0]y;
and16 dut(y, ta, tb); and16 dut(y, ta, tb);
initial begin initial begin
ta = 15'b000000000000000; tb = 15'b000000000000000;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y); $monitor("IN: %b, %b ", ta, tb, "OUT: ", y);
#5 ta = 15'b011010010110010; tb = 15'b000000000000000;
$monitor("IN: %b, %b ", ta, tb, "OUT: ", y);
#5 ta = 15'b000000000000000; tb = 15'b100010110101110;
$monitor("IN: %b, %b ", ta, tb, "OUT: ", y);
#5 ta = 15'b111111111111111; tb = 15'b111111111111111;
$monitor("IN: %b, %b ", ta, tb, "OUT: ", y);
end end
endmodule endmodule