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various fixes

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This commit is contained in:
Erick
2022-03-04 01:38:03 +01:00
parent f598d2d71b
commit 53170f5c5a
25 changed files with 65 additions and 264 deletions
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gates/README.md
-10
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@@ -1,10 +0,0 @@
## Gates
Logic gates are the lowest level from which this project will be implemented.
There are different gates, most of which also have a 16-bit version and eventually a n-way version (even in 16-bit).
All the logic gates are written in Verilog
### Predefined gates
The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes.
### Testbenches
Testbenches are a way to test the implementation of a particular gate using a Verilog compiler
gates/and16.v
+19 -19
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@@ -1,22 +1,22 @@
module and16(y16, a16, b16);
input [15:0] a16;
input [15:0] b16;
output [15:0] y16;
input [15:0]a16;
input [15:0]b16;
output [15:0]y16;
and(y16[0], a16[0], b16[0]);
and(y16[1], a16[1], b16[1]);
and(y16[2], a16[2], b16[2]);
and(y16[3], a16[3], b16[3]);
and(y16[4], a16[4], b16[4]);
and(y16[5], a16[5], b16[5]);
and(y16[6], a16[6], b16[6]);
and(y16[7], a16[7], b16[7]);
and(y16[8], a16[8], b16[8]);
and(y16[9], a16[9], b16[9]);
and(y16[10], a16[10], b16[10]);
and(y16[11], a16[11], b16[11]);
and(y16[12], a16[12], b16[12]);
and(y16[13], a16[13], b16[13]);
and(y16[14], a16[14], b16[14]);
and(y16[15], a16[15], b16[15]);
and and0(y16[0], a16[0], b16[0]);
and and1(y16[1], a16[1], b16[1]);
and and2(y16[2], a16[2], b16[2]);
and and3(y16[3], a16[3], b16[3]);
and and4(y16[4], a16[4], b16[4]);
and and5(y16[5], a16[5], b16[5]);
and and6(y16[6], a16[6], b16[6]);
and and7(y16[7], a16[7], b16[7]);
and and8(y16[8], a16[8], b16[8]);
and and9(y16[9], a16[9], b16[9]);
and and10(y16[10], a16[10], b16[10]);
and and11(y16[11], a16[11], b16[11]);
and and12(y16[12], a16[12], b16[12]);
and and13(y16[13], a16[13], b16[13]);
and and14(y16[14], a16[14], b16[14]);
and and15(y16[15], a16[15], b16[15]);
endmodule
gates/and8way.v
+7 -7
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@@ -3,13 +3,13 @@ module and8way(out, i0, i1, i2, i3, i4, i5, i6, i7);
output out;
wire tmp01, tmp23, tmp45, tmp67, tmp0123, tmp4567;
and(tmp01, i0, i1);
and(tmp23, i2, i3);
and(tmp45, i4, i5);
and(tmp67, i6, i7);
and andA(tmp01, i0, i1);
and andB(tmp23, i2, i3);
and andC(tmp45, i4, i5);
and andD(tmp67, i6, i7);
and(tmp0123, tmp01, tmp23);
and(tmp4567, tmp45, tmp67);
and andAB(tmp0123, tmp01, tmp23);
and andCD(tmp4567, tmp45, tmp67);
and(out, tmp0123, tmp4567);
and andFinal(out, tmp0123, tmp4567);
endmodule
gates/and8way16.v
+9 -9
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@@ -1,4 +1,4 @@
include "and16.v"
'include "and16.v"
module and8way16(out, i0, i1, i2, i3, i4, i5, i6, i7);
input [15:0]i0;
@@ -9,7 +9,7 @@ module and8way16(out, i0, i1, i2, i3, i4, i5, i6, i7);
input [15:0]i5;
input [15:0]i6;
input [15:0]i7;
output [15:0] out;
output [15:0]out;
wire [15:0]tmp01;
wire [15:0]tmp23;
wire [15:0]tmp45;
@@ -17,13 +17,13 @@ module and8way16(out, i0, i1, i2, i3, i4, i5, i6, i7);
wire [15:0]tmp0123;
wire [15:0]tmp4567;
and16 and01(tmp01, i0, i1);
and16 and23(tmp23, i2, i3);
and16 and45(tmp45, i4, i5);
and16 and67(tmp67, i6, i7);
and16 andA(tmp01, i0, i1);
and16 andB(tmp23, i2, i3);
and16 andC(tmp45, i4, i5);
and16 andD(tmp67, i6, i7);
and16 and0123(tmp0123, tmp01, tmp23);
and16 and4567(tmp4567, tmp45, tmp67);
and16 andAB(tmp0123, tmp01, tmp23);
and16 andCD(tmp4567, tmp45, tmp67);
and16 final(out, tmp0123, tmp4567);
and16 andFinal(out, tmp0123, tmp4567);
endmodule
gates/demux4way.v
+4 -4
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@@ -1,12 +1,12 @@
include "demux.v";
'include "demux.v"
module demux4way(out0, out1, out2, out3, i0, i1, sel);
input i0, i1;
input [3:0] sel;
input [1:0] sel;
output out0, out1, out2, out3;
wire [3:0] [1:0] sel0 = sel;
wire [0:3] [1:0] sel1 = sel;
wire [1:0] [1:0] sel0 = sel;
wire [0:1] [1:0] sel1 = sel;
demux(out0, out1, i0, sel0);
demux(out2, out3, i1, sel1);
gates/demux4way16.v
+1 -1
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@@ -1,4 +1,4 @@
include "demux.v";
'include "demux.v"
module demux4way(out0, out1, out2, out3, i0, i1, sel);
input [15:0]i0;
gates/demux8way.v
+1 -1
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@@ -1,4 +1,4 @@
include "demux4way.v";
'include "demux4way.v"
module demux8way(out0, out1, out3, out4, out5, out6, out7, i0, i1, i2, i3, sel);
input i0, i1, i2, i3;
gates/demux8way16.v
+1 -1
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@@ -1,4 +1,4 @@
include "demux4way16.v";
'include "demux4way16.v"
module demux8way(out0, out1, out3, out4, out5, out6, out7, i0, i1, i2, i3, sel);
input [15:0]i0;
gates/mux4way.v
+12 -8
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@@ -1,18 +1,22 @@
include "mux.v";
include "or4way.v";
'include "mux.v"
'include "or4way.v"
module mux4way(out, i0, i1, i2, i3, sel0, sel1);
input i0, i1, i2, i3;
input [2:0]sel;
input [3:0]sel;
output [3:0]out;
wire tmp0, tmp1, tmp2, tmp3;
not(notSel, sel);
wire [3:0] [1:0] sel0 = sel;
wire [0:3] [1:0] sel1 = sel;
and(tmp0, i0, notSel);
and(tmp1, i1, sel);
and(tmp2, i2, notSel);
and(tmp3, i3, sel);
not(notSel0, sel0);
not(notSel1, sel1);
and(tmp0, i0, notSel0);
and(tmp1, i1, sel0);
and(tmp2, i2, notSel1);
and(tmp3, i3, sel1);
or4way(out, tmp0, tmp1, tmp2, tmp3);
gates/mux4way16.v
+4 -4
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@@ -1,13 +1,13 @@
include "and16.v"
include "not16.v"
include "or4way.v"
'include "and16.v"
'include "not16.v"
'include "or4way.v"
module mux4way16(out, i0, i1, i2, i3, sel);
input [15:0]i0;
input [15:0]i1;
input [15:0]i2;
input [15:0]i3;
input [2:0]sel;
input [1:0]sel;
output [15:0]out;
wire [15:0]tmp0;
wire [15:0]tmp1;
gates/mux8way16.v
+5 -5
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@@ -1,5 +1,5 @@
include "mux4way16.v";
include "mux16.v";
'include "mux4way16.v"
'include "mux16.v"
module mux8way16(out, i0, i1, i2, i3, i4, i5, i6, i7, sel);
input [15:0]i0;
@@ -10,12 +10,12 @@ module mux8way16(out, i0, i1, i2, i3, i4, i5, i6, i7, sel);
input [15:0]i5;
input [15:0]i6;
input [15:0]i7;
input [3:0]sel;
input [7:0]sel;
output [15:0]out;
wire tmpMux1, tmpMux1;
wire [3:0] [1:0] sel0 = sel;
wire [0:3] [1:0] sel1 = sel;
wire [7:0] [3:0] sel0 = sel;
wire [0:7] [3:0] sel1 = sel;
mux4way16(tmpMux0, i0, i1, i2, i3, sel0);
mux4way16(tmpMux1, i4, i5, i6, i7, sel1);
gates/or8way.v
+1 -1
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@@ -1,4 +1,4 @@
include "or4way.v";
'include "or4way.v"
module or8way(out4, i0, i1, i2, i3, i4, i5, i6, i7);
input i0, i1, i2, i3, i4, i5, i6, i7;
gates/or8way16.v
+1 -1
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@@ -1,4 +1,4 @@
include "or16.v"
'include "or16.v"
module or8way16(out, i0, i1, i2, i3, i4, i5, i6, i7);
input [15:0]i0;
gates/testbench/and16_tb.v
-16
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@@ -1,16 +0,0 @@
include "predefined/and16.v"
module and_tb();
reg ta,tb;
wire ty;
and_gate dut(y, ta, tb);
initial begin
ta = 0'b16;
tb = 0'b16;
i=0
for(i<=15, i=i+1)
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
ta = ta+1;
tb = tb+1;
end
endmodule
gates/testbench/and_tb.v
-17
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@@ -1,17 +0,0 @@
include "predefined/and_gate.v"
module and_tb();
reg ta,tb;
wire ty;
and_gate dut(y, ta, tb);
initial begin
ta = 0; tb = 0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
#5 ta = 1; tb = 0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
#5 ta = 0; tb = 1;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
#5 ta = 1; tb = 1;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
end
endmodule
gates/testbench/demux_tb.v
-20
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@@ -1,20 +0,0 @@
include "predefined/demux.v"
module demux_tb();
reg a,b, sel;
output y;
demux dut(y, z, a, sel);
initial begin
a = 0; sel = 0;
$monitor("IN: %b ",a, "SEL: ",sel, " OUT: a: %b, b: %b", y, z);
#5;
a = 1;sel = 0;
$monitor("IN: %b ",a, "SEL: ",sel, " OUT: a: %b, b: %b", y, z);
#5;
a = 0; sel = 1;
$monitor("IN: %b ",a, "SEL: ",sel, " OUT: a: %b, b: %b", y, z);
#5;
a = 1; sel = 1;
$monitor("IN: %b ",a, "SEL: ",sel, " OUT: a: %b, b: %b", y, z);
end
endmodule
gates/testbench/mux_tb.v
-32
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@@ -1,32 +0,0 @@
include "predefined/mux.v"
module mux_tb();
reg a,b, sel;
output y;
mux dut(a, b, sel, y);
initial begin
a = 0; b = 0; sel = 0;
$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
#5;
a = 1; b = 0; sel = 0;
$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
#5;
a = 0; b = 1; sel = 0;
$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
#5;
a = 1; b = 1; sel = 0;
$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
#5;
a = 0; b = 0; sel = 1;
$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
#5;
a = 1; b = 0; sel = 1;
$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
#5;
a = 0; b = 1; sel = 1;
$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
#5;
a = 1; b = 1; sel = 1;
$monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
end
endmodule
gates/testbench/nand_tb.v
-17
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@@ -1,17 +0,0 @@
include "predefined/nand_gate.v"
module nand_tb();
reg ta,tb;
wire ty;
nand_gate dut(y, ta, tb);
initial begin
ta = 0; tb = 0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
#5 ta = 1; tb = 0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
#5 ta = 0; tb = 1;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
#5 ta = 1; tb = 1;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
end
endmodule
gates/testbench/nor_tb.v
-18
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@@ -1,18 +0,0 @@
include "predefined/nor_gate.v"
module nor_tb();
reg ta, tb;
wire ty;
nor_gate dut(y, ta, tb);
initial begin
ta=0, tb=0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
ta=0, tb=1;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
ta=1, tb=0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
ta=1, tb=1;
end
endmodule
gates/testbench/not_tb.v
-15
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@@ -1,15 +0,0 @@
include "predefined/not_gate.v"
module not_tb();
reg ta;
wire ty;
not_gate dut(y, ta);
initial begin
ta=0;
$monitor("IN: %b", ta, "OUT: ", y)
ta=1;
$monitor("IN: %b", ta, "OUT: ", y)
end
endmodule
gates/testbench/or_tb.v
-18
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@@ -1,18 +0,0 @@
include "predefined/or_gate.v"
module or_tb();
reg ta, tb;
wire ty;
or_gate dut(y, ta, tb);
initial begin
ta=0, tb=0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
ta=0, tb=1;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
ta=1, tb=0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
ta=1, tb=1;
end
endmodule
gates/testbench/xnor_tb.v
-18
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@@ -1,18 +0,0 @@
include "predefined/xnor_gate.v"
module xnor_tb();
reg ta, tb;
wire ty;
xnor_gate dut(y, ta, tb);
initial begin
ta=0, tb=0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
ta=0, tb=1;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
ta=1, tb=0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
ta=1, tb=1;
end
endmodule
gates/testbench/xor_tb.v
-18
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@@ -1,18 +0,0 @@
include "predefined/nor_gate.v"
module nor_tb();
reg ta, tb;
wire ty;
nor_gate dut(y, ta, tb);
initial begin
ta=0, tb=0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
ta=0, tb=1;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
ta=1, tb=0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
ta=1, tb=1;
end
endmodule
gates/xnor16.v
-2
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@@ -1,5 +1,3 @@
`default_nettype none
module or16(y16, a16, b16);
input [15:0] a16;
input [15:0] b16;
gates/xor16.v
-2
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@@ -1,5 +1,3 @@
`default_nettype none
module xor16(y16, a16, b16);
input [15:0] a16;
input [15:0] b16;