creation of an ALU

cpu/alu/adder.sv

@@ -0,0 +1,18 @@
+'include "cpu/alu/halfadder.sv"
+
+module adder (
+    output sum_bit,
+    output carry_bit,
+    input a,
+    input b,
+    input c
+);
+
+halfadder halfadd(tmpXor0, tmpAnd0, a, b);
+
+xor sum_final(sum_bit, tmpXor0, c);
+
+and carry_tmp0(tmpAnd1, tmpXor0, c);
+or carry_final(carry_bit, tmpAnd0, tmpAnd1);
+
+endmodule

cpu/alu/adder16.sv

@@ -0,0 +1,20 @@
+'include "cpu/alu/adder.sv"
+
+module adder16 (
+    output [15:0]sum_bit,
+    output [15:0]carry_bit
+    input [15:0]a,
+    input [15:0]b,
+    input [15:0]c,
+);
+
+halfadder(tmpXor0, tmpAnd0, a, b)
+
+xor sum_final(sum_bit, tmpXor0, c);
+
+and carry_tmp0(tmpAnd1, tmpXor0, c);
+or carry_final(carry_bit, tmpAnd0, tmpAnd1);
+
+endmodule
+
+

cpu/alu/halfadder.sv

@@ -0,0 +1,11 @@
+module halfadder (
+    output sum_bit,
+    output carry_bit,
+    input a,
+    input b
+);
+
+xor sum_g(sum_bit, a, b);
+and carry_g(carry_bit, a, b);
+
+endmodule