creation of an ALU

2022-03-04 01:39:07 +01:00
parent 52c7210d0c
commit 613178fc34
4 changed files with 49 additions and 0 deletions
@@ -0,0 +1,11 @@
+module halfadder (
+    output sum_bit,
+    output carry_bit,
+    input a,
+    input b
+);
+
+xor sum_g(sum_bit, a, b);
+and carry_g(carry_bit, a, b);
+
+endmodule