verilog predefined gates (re)definition

gates/predefined/and_gate.v

@@ -1,12 +1,12 @@
-module and_gate(a, b, y);
+module and_gate(y, a, b);
     input a, b;
     output y;
 
     always @ (a or b)begin
-        if(a==1'b1 and b==1'b1)begin
+        if(a==1'b1 & b==1'b1)begin
             y=1'b1;
         end
         else
-            y=0'b0;
+            y=1'b0;
     end
 endmodule

gates/predefined/nand_gate.v

@@ -0,0 +1,8 @@
+module nand_gate(y, a, b);
+    input a, b;
+    output y;
+    wire tmpAnd;
+
+    and(tmpAnd, a, b);
+    not(y, tmpAnd);
+endmodule

gates/predefined/nor_gate.v

@@ -1,13 +1,11 @@
 include "or_gate.v"
 include "not_gate.v"
 
-module nor_gate(a, b, y);
+module nor_gate(y, a, b);
     input a, b;
     output y;
-    logic sel;
+    wire sel;
 
-    always @ (a or b)begin
-        or_gate(a, b, sel);
-        not_gate(sel, y);
-    end
+    or_gate(a, b, sel);
+    not_gate(sel, y);
 endmodule

gates/predefined/not_gate.v

@@ -1,4 +1,4 @@
-module not_gate(a, y);
+module not_gate(y, a);
     input a;
     output y;
 

gates/predefined/or_gate.v

@@ -1,9 +1,9 @@
-module or_gate(a, b, y);
+module or_gate(y, a, b);
     input a, b;
     output y;
 
     always @ (a or b)begin
-        if(a==0'b0 and b==0'b0)begin
+        if(a==0'b0 & b==0'b0)begin
             y=0'b0;
         end
         else

gates/predefined/xnor_gate.v

@@ -1,17 +1,16 @@
 include "and_gate.v"
-include "nor_gate.v"
+include "or_gate.v"
 include "not_gate.v"
 
-module xnor_gate(a, b, y);
+module xnor_gate(y, a, b);
     input a, b;
     output y;
-    logic selA, selB, tmpNorA, tmpNorB;
+    wire selA, selB, tmpOrA, tmpOrB, tmpNot;
 
-    always @ (a or b)begin
-        not_gate(a, selA);
-        not_gate(b, selB);
-        and_gate(a, selB, tmpNorA)
-        and_gate(selA, b, tmpNorB)
-        nor_gate(tmpNorA, tmpNorB, y)
-    end
+    not_gate(a, selA);
+    not_gate(b, selB);
+    and_gate(a, selB, tmpOrA);
+    and_gate(selA, b, tmpOrB);
+    or_gate(tmpOrA, tmpOrB, tmpNot);
+    not_gate(tmpNot, y);
 endmodule

gates/predefined/xor_gate.v

@@ -2,16 +2,14 @@ include "and_gate.v"
 include "or_gate.v"
 include "not_gate.v"
 
-module xnor_gate(a, b, y);
+module xor_gate(y, a, b);
     input a, b;
     output y;
-    logic selA, selB, tmpOrA, tmpOrB;
+    wire selA, selB, tmpOrA, tmpOrB;
 
-    always @ (a or b)begin
-        not_gate(a, selA);
-        not_gate(b, selB);
-        and_gate(a, selB, tmpOrA);
-        and_gate(selA, b, tmpOrB);
-        or_gate(tmpOrA, tmpOrB, y);
-    end
+    not_gate(a, selA);
+    not_gate(b, selB);
+    and_gate(a, selB, tmpOrA);
+    and_gate(selA, b, tmpOrB);
+    or_gate(tmpOrA, tmpOrB, y);
 endmodule

gates/testbench/and_tb.v

@@ -1 +1,17 @@
-include "gates/and.v"
+include "and_gate.v"
+
+module and_tb();
+    reg ta,tb;
+    wire ty;
+    and_gate dut(y, ta, tb);
+        initial begin
+            ta = 0; tb = 0;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        #5  ta = 1; tb = 0;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        #5  ta = 0; tb = 1;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        #5  ta = 1; tb = 1;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        end
+endmodule