verilog predefined gates (re)definition

2022-02-28 23:53:53 +01:00
parent e6e955a3b1
commit 680094e4e8
8 changed files with 51 additions and 32 deletions
@@ -1,12 +1,12 @@
-module and_gate(a, b, y);
+module and_gate(y, a, b);
    input a, b;
    output y;

    always @ (a or b)begin
-        if(a==1'b1 and b==1'b1)begin
+        if(a==1'b1 & b==1'b1)begin
            y=1'b1;
        end
        else
-            y=0'b0;
+            y=1'b0;
    end
 endmodule