verilog predefined gates (re)definition

2022-02-28 23:53:53 +01:00
parent e6e955a3b1
commit 680094e4e8
8 changed files with 51 additions and 32 deletions
@@ -0,0 +1,8 @@
+module nand_gate(y, a, b);
+    input a, b;
+    output y;
+    wire tmpAnd;
+
+    and(tmpAnd, a, b);
+    not(y, tmpAnd);
+endmodule