verilog predefined gates (re)definition

2022-02-28 23:53:53 +01:00
parent e6e955a3b1
commit 680094e4e8
8 changed files with 51 additions and 32 deletions
@@ -1,13 +1,11 @@
 include "or_gate.v"
 include "not_gate.v"

-module nor_gate(a, b, y);
+module nor_gate(y, a, b);
    input a, b;
    output y;
-    logic sel;
+    wire sel;

-    always @ (a or b)begin
-        or_gate(a, b, sel);
-        not_gate(sel, y);
-    end
+    or_gate(a, b, sel);
+    not_gate(sel, y);
 endmodule