Archived
1
0

verilog predefined gates (re)definition

This commit is contained in:
Erick
2022-02-28 23:53:53 +01:00
parent e6e955a3b1
commit 680094e4e8
8 changed files with 51 additions and 32 deletions
+1 -1
View File
@@ -1,4 +1,4 @@
module not_gate(a, y);
module not_gate(y, a);
input a;
output y;