verilog predefined gates (re)definition

gates/predefined/or_gate.v

@@ -1,9 +1,9 @@
-module or_gate(a, b, y);
+module or_gate(y, a, b);
     input a, b;
     output y;
 
     always @ (a or b)begin
-        if(a==0'b0 and b==0'b0)begin
+        if(a==0'b0 & b==0'b0)begin
             y=0'b0;
         end
         else