eeeck/iceberg
Archived
1
0
Fork 0
Code Activity

verilog predefined gates (re)definition

Browse Source
This commit is contained in:
Erick
2022-02-28 23:53:53 +01:00
parent e6e955a3b1
commit 680094e4e8
8 changed files with 51 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files
gates/predefined/xnor_gate.v
+9 -10
View File
@@ -1,17 +1,16 @@
include "and_gate.v"
include "nor_gate.v"
include "or_gate.v"
include "not_gate.v"
module xnor_gate(a, b, y);
module xnor_gate(y, a, b);
input a, b;
output y;
logic selA, selB, tmpNorA, tmpNorB;
wire selA, selB, tmpOrA, tmpOrB, tmpNot;
always @ (a or b)begin
not_gate(a, selA);
not_gate(b, selB);
and_gate(a, selB, tmpNorA)
and_gate(selA, b, tmpNorB)
nor_gate(tmpNorA, tmpNorB, y)
end
not_gate(a, selA);
not_gate(b, selB);
and_gate(a, selB, tmpOrA);
and_gate(selA, b, tmpOrB);
or_gate(tmpOrA, tmpOrB, tmpNot);
not_gate(tmpNot, y);
endmodule