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verilog predefined gates (re)definition

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Erick
2022-02-28 23:53:53 +01:00
parent e6e955a3b1
commit 680094e4e8
8 changed files with 51 additions and 32 deletions
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gates/predefined/xor_gate.v
+7 -9
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@@ -2,16 +2,14 @@ include "and_gate.v"
include "or_gate.v"
include "not_gate.v"
module xnor_gate(a, b, y);
module xor_gate(y, a, b);
input a, b;
output y;
logic selA, selB, tmpOrA, tmpOrB;
wire selA, selB, tmpOrA, tmpOrB;
always @ (a or b)begin
not_gate(a, selA);
not_gate(b, selB);
and_gate(a, selB, tmpOrA);
and_gate(selA, b, tmpOrB);
or_gate(tmpOrA, tmpOrB, y);
end
not_gate(a, selA);
not_gate(b, selB);
and_gate(a, selB, tmpOrA);
and_gate(selA, b, tmpOrB);
or_gate(tmpOrA, tmpOrB, y);
endmodule