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verilog predefined gates (re)definition

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Erick
2022-02-28 23:53:53 +01:00
parent e6e955a3b1
commit 680094e4e8
8 changed files with 51 additions and 32 deletions
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gates/testbench/and_tb.v
+17 -1
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@@ -1 +1,17 @@
include "gates/and.v"
include "and_gate.v"
module and_tb();
reg ta,tb;
wire ty;
and_gate dut(y, ta, tb);
initial begin
ta = 0; tb = 0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
#5 ta = 1; tb = 0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
#5 ta = 0; tb = 1;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
#5 ta = 1; tb = 1;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
end
endmodule