output size fix

memory/ram/ram4096.sv

@@ -0,0 +1,50 @@
+import ram512::*;
+
+package ram4096 (
+    input [4095:0]in;
+    input [11:0]addr;
+    input load;
+    input clk
+    output [4095:0]out;
+);
+
+wire     [511:0] [511:0] in0 = in;
+wire  [1023:511] [511:0] in1 = in;
+wire [1535:1023] [511:0] in2 = in;
+wire [2047:1535] [511:0] in3 = in;
+wire [2559:2047] [511:0] in4 = in;
+wire [3071:2559] [511:0] in5 = in;
+wire [3583:3071] [511:0] in6 = in;
+wire [4095:3583] [511:0] in7 = in;
+
+wire [11:0] [8:0] addr0 = in;
+wire [0:11] [8:0] addr1 = in;
+
+wire [511:0]out0;
+wire [511:0]out1;
+wire [511:0]out2;
+wire [511:0]out3;
+wire [511:0]out4;
+wire [511:0]out5;
+wire [511:0]out6;
+wire [511:0]out7;
+
+ram512 clstr0(in0, addr0, load, clk, out0);
+ram512 clstr1(in1, addr0, load, clk, out1);
+ram512 clstr2(in2, addr0, load, clk, out2);
+ram512 clstr3(in3, addr0, load, clk, out3);
+ram512 clstr4(in4, addr1, load, clk, out4);
+ram512 clstr5(in5, addr1, load, clk, out5);
+ram512 clstr6(in6, addr1, load, clk, out6);
+ram512 clstr7(in7, addr1, load, clk, out7);
+
+wire [511:0]     [511:0] out0 = out;
+wire [511:0]  [1023:511] out1 = out;
+wire [511:0] [1535:1023] out2 = out;
+wire [511:0] [2047:1535] out3 = out;
+wire [511:0] [2559:2047] out4 = out;
+wire [511:0] [3071:2559] out5 = out;
+wire [511:0] [3583:3071] out6 = out;
+wire [511:0] [4095:3583] out7 = out;
+
+endpackage

memory/ram/ram512.sv

@@ -110,38 +110,37 @@ ram16 clstr29(in29, addr1, load, clk, out29);
 ram16 clstr30(in30, addr1, load, clk, out30);
 ram16 clstr31(in31, addr1, load, clk, out31);
 
-wire [15:0]    [511:0]  out0 = out;
-wire [31:15]   [511:0]  out1 = out;
-wire [47:31]   [511:0]  out2 = out;
-wire [63:47]   [511:0]  out3 = out;
-wire [79:63]   [511:0]  out4 = out;
-wire [95:79]   [511:0]  out5 = out;
-wire [111:95]  [511:0]  out6 = out;
-wire [127:111] [511:0]  out7 = out;
-wire [143:127] [511:0]  out8 = out;
-wire [159:143] [511:0]  out9 = out;
-wire [179:159] [511:0]  out10 = out;
-wire [191:179] [511:0]  out11 = out;
-wire [207:191] [511:0]  out12 = out;
-wire [223:207] [511:0]  out13 = out;
-wire [239:223] [511:0]  out14 = out;
-wire [255:239] [511:0]  out15 = out;
-wire [271:255] [511:0]  out16 = out;
-wire [287:271] [511:0]  out17 = out;
-wire [303:287] [511:0]  out18 = out;
-wire [319:303] [511:0]  out19 = out;
-wire [335:319] [511:0]  out20 = out;
-wire [351:335] [511:0]  out21 = out;
-wire [367:351] [511:0]  out22 = out;
-wire [383:367] [511:0]  out23 = out;
-wire [399:383] [511:0]  out24 = out;
-wire [415:399] [511:0]  out25 = out;
-wire [431:415] [511:0]  out26 = out;
-wire [447:431] [511:0]  out27 = out;
-wire [463:447] [511:0]  out28 = out;
-wire [479:463] [511:0]  out29 = out;
-wire [495:479] [511:0]  out30 = out;
-wire [511:495] [511:0]  out31 = out;
-
+wire [15:0]    [15:0] out0 = out;
+wire [15:0]   [31:15] out1 = out;
+wire [15:0]   [47:31] out2 = out;
+wire [15:0]   [63:47] out3 = out;
+wire [15:0]   [79:63] out4 = out;
+wire [15:0]   [95:79] out5 = out;
+wire [15:0]  [111:95] out6 = out;
+wire [15:0] [127:111] out7 = out;
+wire [15:0] [143:127] out8 = out;
+wire [15:0] [159:143] out9 = out;
+wire [15:0] [179:159] out10 = out;
+wire [15:0] [191:179] out11 = out;
+wire [15:0] [207:191] out12 = out;
+wire [15:0] [223:207] out13 = out;
+wire [15:0] [239:223] out14 = out;
+wire [15:0] [255:239] out15 = out;
+wire [15:0] [271:255] out16 = out;
+wire [15:0] [287:271] out17 = out;
+wire [15:0] [303:287] out18 = out;
+wire [15:0] [319:303] out19 = out;
+wire [15:0] [335:319] out20 = out;
+wire [15:0] [351:335] out21 = out;
+wire [15:0] [367:351] out22 = out;
+wire [15:0] [383:367] out23 = out;
+wire [15:0] [399:383] out24 = out;
+wire [15:0] [415:399] out25 = out;
+wire [15:0] [431:415] out26 = out;
+wire [15:0] [447:431] out27 = out;
+wire [15:0] [463:447] out28 = out;
+wire [15:0] [479:463] out29 = out;
+wire [15:0] [495:479] out30 = out;
+wire [15:0] [511:495] out31 = out;
 
 endpackage

memory/ram/ram64.sv

@@ -38,13 +38,13 @@ ram8 clstr5(in5, addr1, load, clk, out5);
 ram8 clstr6(in6, addr1, load, clk, out6);
 ram8 clstr7(in7, addr1, load, clk, out7);
 
-wire   [7:0] [63:0] out0 = out;
-wire  [15:8] [63:0] out1 = out;
-wire [24:15] [63:0] out2 = out;
-wire [31:24] [63:0] out3 = out;
-wire [39:31] [63:0] out4 = out;
-wire [47:39] [63:0] out5 = out;
-wire [55:47] [63:0] out6 = out;
-wire [63:55] [63:0] out7 = out;
+wire [7:0]   [7:0] out0 = out;
+wire [7:0]  [15:8] out1 = out;
+wire [7:0] [24:15] out2 = out;
+wire [7:0] [31:24] out3 = out;
+wire [7:0] [39:31] out4 = out;
+wire [7:0] [47:39] out5 = out;
+wire [7:0] [55:47] out6 = out;
+wire [7:0] [63:55] out7 = out;
 
 endpackage