minor fixes in flipflop logic

gates/nand3way.v

@@ -0,0 +1,13 @@
+module nand3way(y16, a16, b16, c16);
+    input a16;
+    input b16;
+    input c16;
+    output y16;
+
+    wire tmp0, tmp1
+
+    nand(tmp0, a16, b16);
+    nand(tmp1, tmp0, tmp0);
+    nand(y16, tmp1, c16);
+
+endmodule

gates/nand3way16.v

@@ -1,15 +0,0 @@
-'include "gates/nand16.v"
-
-module nand3way16(y16, a16, b16, c16);
-    input [15:0]a16;
-    input [15:0]b16;
-    input [15:0]c16;
-    output [15:0]y16;
-
-    wire tmp0[15:0], tmp1[15:0]
-
-    nand16(tmp0, a16, b16);
-    nand16(tmp1, tmp0, tmp0);
-    nand16(y16, tmp1, c16);
-
-endmodule

memory/flipflop/d_flipflop.sv

@@ -1,14 +1,12 @@
-'include "gates/nand3way16.v"
-
 import sr_flipflop::*;
 
 package d_flipflop (
-    output [15:0]dq, [15:0]dq_compl
-    input [15:0]d, clk,
+    output dq, dq_compl
+    input d, clk,
 );
 
-nand16(tmp0, d, clk);
-nand16(tmp1, clk, tmp0);
+nand(tmp0, d, clk);
+nand(tmp1, clk, tmp0);
 
 sr_flipflop(dq, dq_compl, tmp0, tmp1);
 

memory/flipflop/jk_flipflop.sv

@@ -1,14 +1,14 @@
-'include "gates/nand3way16.v"
+'include "gates/nand3way.v"
 
 import sr_flipflop::*;
 
 package jk_flipflop (
-    output [15:0]jkq, [15:0]jkq_compl
-    input [15:0]j, [15:0]k, [15:0]clk   //FIXME: is 26bit clock correct? Like can it go only as 0000000000000000 and 1111111111111111?
+    output jkq, jkq_compl
+    input j, k, clk
 );
 
-nand3way16(notS, jkq_compl, j, clk);
-nand3way16(notR, jkq, k, clk);
+nand3way(notS, jkq_compl, j, clk);
+nand3way(notR, jkq, k, clk);
 
 sr_flipflop(jkq, jkq_compl, notS, notR);
 

memory/flipflop/sr_flipflop.sv

@@ -1,11 +1,9 @@
-'include "gates/nand16.v"
-
 package sr_flipflop (
-    output [15:0]srq, [15:0]srq_compl
-    input [15:0]s, [15:0]r
+    output srq, srq_compl
+    input s, r
 );
 
-nand16 nand0(q, s, q_compl);
-nand16 nand1(q_compl, r, q);
+nand(q, s, q_compl);
+nand(q_compl, r, q);
 
 endpackage