minor fixes in flipflop logic

2022-03-08 15:07:02 +01:00
parent bfb055ed87
commit 8c70d4384f
5 changed files with 26 additions and 32 deletions
@@ -0,0 +1,13 @@
+module nand3way(y16, a16, b16, c16);
+    input a16;
+    input b16;
+    input c16;
+    output y16;
+
+    wire tmp0, tmp1
+
+    nand(tmp0, a16, b16);
+    nand(tmp1, tmp0, tmp0);
+    nand(y16, tmp1, c16);
+
+endmodule
@@ -1,15 +0,0 @@
-'include "gates/nand16.v"
-
-module nand3way16(y16, a16, b16, c16);
-    input [15:0]a16;
-    input [15:0]b16;
-    input [15:0]c16;
-    output [15:0]y16;
-
-    wire tmp0[15:0], tmp1[15:0]
-
-    nand16(tmp0, a16, b16);
-    nand16(tmp1, tmp0, tmp0);
-    nand16(y16, tmp1, c16);
-
-endmodule