minor fixes in flipflop logic

memory/flipflop/d_flipflop.sv

@@ -1,14 +1,12 @@
-'include "gates/nand3way16.v"
-
 import sr_flipflop::*;
 
 package d_flipflop (
-    output [15:0]dq, [15:0]dq_compl
-    input [15:0]d, clk,
+    output dq, dq_compl
+    input d, clk,
 );
 
-nand16(tmp0, d, clk);
-nand16(tmp1, clk, tmp0);
+nand(tmp0, d, clk);
+nand(tmp1, clk, tmp0);
 
 sr_flipflop(dq, dq_compl, tmp0, tmp1);