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minor fixes in flipflop logic

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This commit is contained in:
Erick
2022-03-08 15:07:02 +01:00
parent bfb055ed87
commit 8c70d4384f
5 changed files with 26 additions and 32 deletions
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memory/flipflop/jk_flipflop.sv
+5 -5
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@@ -1,14 +1,14 @@
'include "gates/nand3way16.v"
'include "gates/nand3way.v"
import sr_flipflop::*;
package jk_flipflop (
output [15:0]jkq, [15:0]jkq_compl
input [15:0]j, [15:0]k, [15:0]clk //FIXME: is 26bit clock correct? Like can it go only as 0000000000000000 and 1111111111111111?
output jkq, jkq_compl
input j, k, clk
);
nand3way16(notS, jkq_compl, j, clk);
nand3way16(notR, jkq, k, clk);
nand3way(notS, jkq_compl, j, clk);
nand3way(notR, jkq, k, clk);
sr_flipflop(jkq, jkq_compl, notS, notR);