created sr, jk and data flipflops

2022-03-08 13:54:42 +01:00
parent a4c9507c3c
commit b5d5fb5a05
4 changed files with 41 additions and 13 deletions
@@ -0,0 +1,15 @@
+'include "gates/nand3way16.v"
+
+import sr_flipflop::*;
+
+package jk_flipflop (
+    output [15:0]jkq, [15:0]jkq_compl
+    input [15:0]j, [15:0]k, [15:0]clk   //FIXME: is 26bit clock correct? Like can it go only as 0000000000000000 and 1111111111111111?
+);
+
+nand3way16(notS, jkq_compl, j, clk);
+nand3way16(notR, jkq, k, clk);
+
+sr_flipflop(jkq, jkq_compl, notS, notR);
+
+endpackage