Create mux.v (multiplexer gate)

2022-02-28 23:56:05 +01:00
parent 90287bca73
commit bcb06dae6a
1 changed files with 10 additions and 0 deletions
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 module mux(y, a, b, sel);
    input a, b, sel;
    inout y;
    wire notSel, andA, andB;
    not(notSel, sel);
    and(andA, a, sel);
    and(andB, b, notSel);
    or(y, andA, andB);
 endmodule