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Erick
2022-03-04 01:42:05 +01:00
parent f0bd0b4a63
commit d259cdab06
1 changed files with 19 additions and 19 deletions
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README.md
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@@ -8,31 +8,30 @@ Logic gates are the lowest level point from which this project is implemented. T
Most of the gates also have a 16-bit version and eventually a n-way version (some even n-way-16-bit).
Ex: a 4-way mux gate:
'''
include "mux.v"
include "or4way.v"
module mux4way(out, i0, i1, i2, i3, sel0, sel1);
input i0, i1, i2, i3;
input [3:0]sel;
output [3:0]out;
wire tmp0, tmp1, tmp2, tmp3;
include "mux.v"
include "or4way.v"
wire [3:0] [1:0] sel0 = sel;
wire [0:3] [1:0] sel1 = sel;
module mux4way(out, i0, i1, i2, i3, sel0, sel1);
input i0, i1, i2, i3;
input [3:0]sel;
output [3:0]out;
wire tmp0, tmp1, tmp2, tmp3;
not(notSel0, sel0);
not(notSel1, sel1);
wire [3:0] [1:0] sel0 = sel;
wire [0:3] [1:0] sel1 = sel;
and(tmp0, i0, notSel0);
and(tmp1, i1, sel0);
and(tmp2, i2, notSel1);
and(tmp3, i3, sel1);
not(notSel0, sel0);
not(notSel1, sel1);
or4way(out, tmp0, tmp1, tmp2, tmp3);
and(tmp0, i0, notSel0);
and(tmp1, i1, sel0);
and(tmp2, i2, notSel1);
and(tmp3, i3, sel1);
endmodule
'''
or4way(out, tmp0, tmp1, tmp2, tmp3);
endmodule
#### Predefined gates (path: /gates/predefined)
The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes.
@@ -41,6 +40,7 @@ The predefined gates are by default implemented on Verilog/Systemverilog. Thus t
Testbenches are a way to test the implementation of a particular gate using a Verilog compiler
Ex: testbench for a xor gate:
'''
include "gates/predefined/xor_gate.v"