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Erick
2022-03-04 01:42:05 +01:00
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README.md
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@@ -8,7 +8,7 @@ Logic gates are the lowest level point from which this project is implemented. T
Most of the gates also have a 16-bit version and eventually a n-way version (some even n-way-16-bit). Most of the gates also have a 16-bit version and eventually a n-way version (some even n-way-16-bit).
Ex: a 4-way mux gate: Ex: a 4-way mux gate:
'''
include "mux.v" include "mux.v"
include "or4way.v" include "or4way.v"
@@ -32,7 +32,6 @@ module mux4way(out, i0, i1, i2, i3, sel0, sel1);
or4way(out, tmp0, tmp1, tmp2, tmp3); or4way(out, tmp0, tmp1, tmp2, tmp3);
endmodule endmodule
'''
#### Predefined gates (path: /gates/predefined) #### Predefined gates (path: /gates/predefined)
The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes. The predefined gates are by default implemented on Verilog/Systemverilog. Thus they are not strictly needed for building more advanced gates or chipset, but I still decided to add them as reference and learning purposes.
@@ -41,6 +40,7 @@ The predefined gates are by default implemented on Verilog/Systemverilog. Thus t
Testbenches are a way to test the implementation of a particular gate using a Verilog compiler Testbenches are a way to test the implementation of a particular gate using a Verilog compiler
Ex: testbench for a xor gate: Ex: testbench for a xor gate:
''' '''
include "gates/predefined/xor_gate.v" include "gates/predefined/xor_gate.v"