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update and debug testbench

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Erick
2022-03-04 01:38:36 +01:00
parent 9c4b6b7ce4
commit d65b968e96
11 changed files with 208 additions and 0 deletions
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testbench/adder_tb.sv
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'include "cpu/alu/adder.sv"
module adder_tb();
reg ta,tb, tc;
wire t_sum, t_carry;
adder dut(t_sum, t_carry, ta, tb, tc);
initial begin
ta = 0; tb = 0; tc = 0;
$monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
#5 ta = 1; tb = 0; tc = 0;
$monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
#5 ta = 0; tb = 1; tc = 0;
$monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
#5 ta = 1; tb = 1; tc = 0;
$monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
#5 ta = 0; tb = 0; tc = 1;
$monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
#5 ta = 1; tb = 0; tc = 1;
$monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
#5 ta = 0; tb = 1; tc = 1;
$monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
#5 ta = 1; tb = 1; tc = 1;
$monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
end
endmodule