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update and debug testbench

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Erick
2022-03-04 01:38:36 +01:00
parent 9c4b6b7ce4
commit d65b968e96
11 changed files with 208 additions and 0 deletions
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testbench/and_tb.v
+17
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'include "predefined/and_gate.v"
module and_tb();
reg ta,tb;
wire ty;
and_gate dut(y, ta, tb);
initial begin
ta = 0; tb = 0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
#5 ta = 1; tb = 0;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
#5 ta = 0; tb = 1;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
#5 ta = 1; tb = 1;
$monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
end
endmodule