update and debug testbench

testbench/adder_tb.sv

@@ -0,0 +1,25 @@
+'include "cpu/alu/adder.sv"
+
+module adder_tb();
+    reg ta,tb, tc;
+    wire t_sum, t_carry;
+    adder dut(t_sum, t_carry, ta, tb, tc);
+        initial begin
+            ta = 0; tb = 0; tc = 0;
+            $monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
+        #5  ta = 1; tb = 0; tc = 0;
+            $monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
+        #5  ta = 0; tb = 1; tc = 0;
+            $monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
+        #5  ta = 1; tb = 1; tc = 0;
+            $monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
+        #5  ta = 0; tb = 0; tc = 1;
+            $monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
+        #5  ta = 1; tb = 0; tc = 1;
+            $monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
+        #5  ta = 0; tb = 1; tc = 1;
+            $monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
+        #5  ta = 1; tb = 1; tc = 1;
+            $monitor("A/B/C: %b, %b, %b ",ta, tb, tc, "S/C: %b, %b",t_sum, t_carry);
+        end
+endmodule

testbench/and16_tb.v

@@ -0,0 +1,11 @@
+'include "predefined/and16.v"
+
+module and_tb();
+    reg [15:0]ta, [15:0]tb;
+    wire [15:0]y;
+    and16 dut(y, ta, tb);
+        initial begin
+            
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        end
+endmodule

testbench/and_tb.v

@@ -0,0 +1,17 @@
+'include "predefined/and_gate.v"
+
+module and_tb();
+    reg ta,tb;
+    wire ty;
+    and_gate dut(y, ta, tb);
+        initial begin
+            ta = 0; tb = 0;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        #5  ta = 1; tb = 0;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        #5  ta = 0; tb = 1;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        #5  ta = 1; tb = 1;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        end
+endmodule

testbench/demux_tb.v

@@ -0,0 +1,20 @@
+'include "predefined/demux.v"
+
+module demux_tb();
+    reg a,b, sel;
+    output y;
+    demux dut(y, z, a, sel);
+        initial begin
+            a = 0; sel = 0;
+            $monitor("IN: %b ",a, "SEL: ",sel, " OUT: a: %b, b: %b", y, z);
+            #5;
+            a = 1;sel = 0;
+            $monitor("IN: %b ",a, "SEL: ",sel, " OUT: a: %b, b: %b", y, z);
+            #5;
+            a = 0; sel = 1;
+            $monitor("IN: %b ",a, "SEL: ",sel, " OUT: a: %b, b: %b", y, z);
+            #5;
+            a = 1; sel = 1;
+            $monitor("IN: %b ",a, "SEL: ",sel, " OUT: a: %b, b: %b", y, z);
+        end
+endmodule

testbench/half_adder_tb.sv

@@ -0,0 +1,17 @@
+'include "cpu/alu/halfadder.sv"
+
+module halfadder_tb();
+    reg ta,tb;
+    wire t_sum, t_carry;
+    halfadder dut(t_sum, t_carry, ta, tb);
+        initial begin
+            ta = 0; tb = 0;
+            $monitor("A/B: %b, %b ",ta, tb, "S/C: %b, %b",t_sum, t_carry);
+        #5  ta = 1; tb = 0;
+            $monitor("A/B: %b, %b ",ta, tb, "S/C: %b, %b",t_sum, t_carry);
+        #5  ta = 0; tb = 1;
+            $monitor("A/B: %b, %b ",ta, tb, "S/C: %b, %b",t_sum, t_carry);
+        #5  ta = 1; tb = 1;
+            $monitor("A/B: %b, %b ",ta, tb, "S/C: %b, %b",t_sum, t_carry);
+        end
+endmodule

testbench/mux_tb.v

@@ -0,0 +1,32 @@
+'include "predefined/mux.v"
+
+module mux_tb();
+    reg a,b, sel;
+    output y;
+    mux dut(a, b, sel, y);
+        initial begin
+            a = 0; b = 0; sel = 0;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+            #5;
+            a = 1; b = 0; sel = 0;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+            #5;
+            a = 0; b = 1; sel = 0;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+            #5;
+            a = 1; b = 1; sel = 0;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+            #5;
+            a = 0; b = 0; sel = 1;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+            #5;
+            a = 1; b = 0; sel = 1;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+            #5;
+            a = 0; b = 1; sel = 1;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+            #5;
+            a = 1; b = 1; sel = 1;
+            $monitor("IN: %b, %b ",a, b, "SEL: ",sel, " OUT: ",y);
+        end
+endmodule

testbench/nand_tb.v

@@ -0,0 +1,17 @@
+'include "predefined/nand_gate.v"
+
+module nand_tb();
+    reg ta,tb;
+    wire ty;
+    nand_gate dut(y, ta, tb);
+        initial begin
+            ta = 0; tb = 0;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        #5  ta = 1; tb = 0;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        #5  ta = 0; tb = 1;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        #5  ta = 1; tb = 1;
+            $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        end
+endmodule

testbench/nor_tb.v

@@ -0,0 +1,18 @@
+'include "predefined/nor_gate.v"
+
+module nor_tb();
+    reg ta, tb;
+    wire ty;
+
+    nor_gate dut(y, ta, tb);
+
+    initial begin
+        ta=0, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=0, tb=1;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=1;
+    end
+endmodule

testbench/not_tb.v

@@ -0,0 +1,15 @@
+'include "predefined/not_gate.v"
+
+module not_tb();
+    reg ta;
+    wire ty;
+
+    not_gate dut(y, ta);
+
+    initial begin
+        ta=0;
+        $monitor("IN: %b", ta, "OUT: ", y)
+        ta=1;
+        $monitor("IN: %b", ta, "OUT: ", y)
+    end
+endmodule

testbench/or_tb.v

@@ -0,0 +1,18 @@
+'include "predefined/or_gate.v"
+
+module or_tb();
+    reg ta, tb;
+    wire ty;
+
+    or_gate dut(y, ta, tb);
+
+    initial begin
+        ta=0, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=0, tb=1;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=1;
+    end
+endmodule

testbench/xnor_tb.v

@@ -0,0 +1,18 @@
+'include "predefined/xnor_gate.v"
+
+module xnor_tb();
+    reg ta, tb;
+    wire ty;
+
+    xnor_gate dut(y, ta, tb);
+
+    initial begin
+        ta=0, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=0, tb=1;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=0;
+        $monitor("IN: %b, %b ",ta, tb, "OUT: ",y);
+        ta=1, tb=1;
+    end
+endmodule