created 16-bit cpu

cpu/cpu.sv

@@ -1 +1,30 @@
-import alu::*;
+import alu::*;
+import pc::*;
+import reg16::*
+
+'include "gates/mux16.v"
+
+package cpu (
+    input [15:0]inM,
+    input [15:0]instr,
+    input reset,
+    input clk,
+    input sel[15:0]
+    output [15:0]outM,
+    output flagM[2:0]
+    output wrtM,
+    output [15:0]addrM,
+    output [15:0]pc
+);
+
+mux16 instrMux(outInstrMux, outM, instr, wrtM);
+reg16 AReg(outInstrMux, wrtM, clk, addrM notOutAReg);
+
+mux16 inputMux(InAlu1, addrM, inM, wrtM);
+reg16 DReg(outM, wrtM, clk, InAlu0, notOut);
+
+alu alu(InAlu0, InAlu1, sel, outM, flagM);
+
+pc pc(addrM, wrtM, reset, clk, pc);
+
+endpackage

memory/counter/pc.sv

@@ -1,9 +1,6 @@
-import d_flipflop::*;
-
 package pc (
     input [15:0]in;
     input load;
-    input inc;
     input reset;
     input clk;
     output [15:0]out;
@@ -16,10 +13,8 @@ if (reset == 1)
     out = zero16;
 else if (load == 1)
     out = in;
-else if (inc == 1)
-    out = out + oneplus16;
 else
-    out = out;
+    out = out + oneplus16;
 end
 
 endpackage