created 16-bit cpu

2022-03-27 18:30:31 +02:00
parent a657c66e09
commit e568e64264
2 changed files with 31 additions and 7 deletions
@@ -1,9 +1,6 @@
-import d_flipflop::*;
-
 package pc (
    input [15:0]in;
    input load;
-    input inc;
    input reset;
    input clk;
    output [15:0]out;
@@ -16,10 +13,8 @@ if (reset == 1)
    out = zero16;
 else if (load == 1)
    out = in;
-else if (inc == 1)
-    out = out + oneplus16;
 else
-    out = out;
+    out = out + oneplus16;
 end

 endpackage