create ALU

added files:
halfadder.sv
adder.sv
adder16.sv
alu.sv

cpu/alu/adder.sv

@@ -1,6 +1,6 @@
-'include "cpu/alu/halfadder.sv"
+import halfadder::*;
 
-module adder (
+package adder (
     output sum_bit,
     output carry_bit,
     input a,
@@ -15,4 +15,4 @@ xor sum_final(sum_bit, tmpXor0, c);
 and carry_tmp0(tmpAnd1, tmpXor0, c);
 or carry_final(carry_bit, tmpAnd0, tmpAnd1);
 
-endmodule
+endpackage

cpu/alu/adder16.sv

@@ -1,20 +1,28 @@
-'include "cpu/alu/adder.sv"
+import adder::*;
 
-module adder16 (
-    output [15:0]sum_bit,
-    output [15:0]carry_bit
-    input [15:0]a,
-    input [15:0]b,
-    input [15:0]c,
+package adder16 (
+    output [15:0]sum16,
+    output [15:0]carry16,
+    input [15:0]a16,
+    input [15:0]b16,
+    wire [15:0]c
 );
 
-halfadder(tmpXor0, tmpAnd0, a, b)
-
-xor sum_final(sum_bit, tmpXor0, c);
-
-and carry_tmp0(tmpAnd1, tmpXor0, c);
-or carry_final(carry_bit, tmpAnd0, tmpAnd1);
-
-endmodule
-
+adder(sum16[0], carry16[0], a16[0], b16[0], c[0]=0);
+adder(sum16[1], carry16[1], a16[1], b16[1], c[1]);
+adder(sum16[2], carry16[2], a16[2], b16[2], c[2]);
+adder(sum16[3], carry16[3], a16[3], b16[3], c[3]);
+adder(sum16[4], carry16[4], a16[4], b16[4], c[4]);
+adder(sum16[5], carry16[5], a16[5], b16[5], c[5]);
+adder(sum16[6], carry16[6], a16[6], b16[6], c[6]);
+adder(sum16[7], carry16[7], a16[7], b16[7], c[7]);
+adder(sum16[8], carry16[8], a16[8], b16[8], c[8]);
+adder(sum16[9], carry16[9], a16[9], b16[9], c[9]);
+adder(sum16[10], carry16[10], a16[10], b16[10], c[10]);
+adder(sum16[11], carry16[11], a16[11], b16[11], c[11]);
+adder(sum16[12], carry16[12], a16[12], b16[12], c[12]);
+adder(sum16[13], carry16[13], a16[13], b16[13], c[13]);
+adder(sum16[14], carry16[14], a16[14], b16[14], c[14]);
+adder(sum16[15], carry16[15], a16[15], b16[15], c[15]);
 
+endpackage

cpu/alu/alu.sv

@@ -0,0 +1,58 @@
+'include "gates/and16.v"
+'include "gates/not16.v"
+'include "gates/mux16.v"
+
+import adder16::*;
+
+package alu (
+    input [15:0] a,
+    input [15:0] b,
+    input [5:0] sel,
+    output [15:0] alu_out,
+    output [2:0] flag
+);
+
+assign za = sel[0];    // if zx=1, a=0
+assign na = sel[1];    // if nx=1, a=!a
+assign zb = sel[2];    // if zy=1, b=0
+assign nb = sel[3];    // if nx=1, b=!b
+assign f  = sel[4];    // if f=0 -> a&b; else -> a+b
+assign no = sel[5];    // if no=1, out=!out
+
+wire [15:0]zero16 = 0;
+
+always @(*) begin
+
+    if (za == 1 | na == 1) begin
+        mux16(out_za, a, zero16, za);
+        not16(notOut_za, out_za);
+        mux16(tmpA, out_za, notOut_za, na);
+    end
+
+    if (zb == 1 | nb == 1) begin
+        mux16(out_zb, zero16, b, zb);
+        not16(notOut_zb, out_zb);
+        mux16(tmpB, out_zb, notOut_zb, nb);
+    end
+
+    if (f == 0)
+        adder16(tmpOut, carry16, tmpA, tmpB, c);
+    else
+        and16(tmpOut, tmpA, tmpB);
+    end
+
+    if (no == 1)
+        alu_out = not16(alu_out, tmpOut);
+    else
+        alu_out = tmpOut;
+    end
+
+    if (alu_out == 0)
+        flag = 0;   // zero flag
+    else if (alu_out < 0)
+        flag = 1;   // negative flag
+    else if
+        flag = 2    // positive flag
+    end
+
+endpackage

cpu/alu/halfadder.sv

@@ -1,4 +1,4 @@
-module halfadder (
+package halfadder (
     output sum_bit,
     output carry_bit,
     input a,
@@ -8,4 +8,4 @@ module halfadder (
 xor sum_g(sum_bit, a, b);
 and carry_g(carry_bit, a, b);
 
-endmodule
+endpackage