create ALU

added files: halfadder.sv adder.sv adder16.sv alu.sv
2022-03-05 00:00:16 +01:00
parent cf48ffa34f
commit f78cc40524
4 changed files with 87 additions and 21 deletions
@@ -1,4 +1,4 @@
-module halfadder (
+package halfadder (
    output sum_bit,
    output carry_bit,
    input a,
@@ -8,4 +8,4 @@ module halfadder (
 xor sum_g(sum_bit, a, b);
 and carry_g(carry_bit, a, b);

-endmodule
+endpackage