Erick
15 lines
411 B
Verilog
15 lines
411 B
Verilog
module and8way(out, i0, i1, i2, i3, i4, i5, i6, i7);
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input i0, i1, i2, i3, i4, i5, i6, i7;
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output out;
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wire tmp01, tmp23, tmp45, tmp67, tmp0123, tmp4567;
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and andA(tmp01, i0, i1);
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and andB(tmp23, i2, i3);
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and andC(tmp45, i4, i5);
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and andD(tmp67, i6, i7);
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and andAB(tmp0123, tmp01, tmp23);
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and andCD(tmp4567, tmp45, tmp67);
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and andFinal(out, tmp0123, tmp4567);
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endmodule |