Erick
22 lines
459 B
Verilog
22 lines
459 B
Verilog
'include "demux.v"
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module demux4way(out0, out1, out2, out3, i0, i1, sel);
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input [15:0]i0;
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input [15:0]i1;
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input [3:0]sel;
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output [15:0]out0;
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output [15:0]out1;
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output [15:0]out2;
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output [15:0]out3;
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wire [3:0] [1:0] sel0 = sel;
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wire [0:3] [1:0] sel1 = sel;
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not(notSel0, sel0);
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not(notSel1, sel1);
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and(out1, i0, sel0);
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and(out0, i0, notSel0);
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and(out2, i1, sel1);
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and(out3, i1, notSel1);
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endmodule |