Erick
15 lines
242 B
Systemverilog
15 lines
242 B
Systemverilog
'include "gates/nand3way.v"
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import sr_flipflop::*;
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package jk_flipflop (
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output jkq, jkq_compl
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input j, k, clk
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);
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nand3way(notS, jkq_compl, j, clk);
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nand3way(notR, jkq, k, clk);
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sr_flipflop(jkq, jkq_compl, notS, notR);
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endpackage |