Erick
35 lines
670 B
Systemverilog
35 lines
670 B
Systemverilog
import alu::*;
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import pc::*;
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import reg16::*
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'include "gates/mux16.v"
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package cpu (
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input [15:0]inM,
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input [15:0]instr,
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input reset,
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input clk,
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output [15:0]outM,
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output [2:0]flagM
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output wrtM,
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output [15:0]addrM,
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output [15:0]pc
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);
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assign wrtM = inM[11:5];
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wire [11:6] [5:0] addrM = sel;
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not(wrtM, notWrtM); //TODO: verify if this is needed
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mux16 instrMux(outInstrMux, outM, instr, wrtM);
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reg16 AReg(outInstrMux, wrtM, clk, addrM, notOutAReg);
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mux16 inputMux(InAlu1, addrM, inM, wrtM);
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reg16 DReg(outM, notWrtM, clk, InAlu0, notOut);
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alu alu(InAlu0, InAlu1, sel, outM, flagM);
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pc pc(addrM, wrtM, reset, clk, pc);
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endpackage |