Erick
12 lines
180 B
Verilog
12 lines
180 B
Verilog
module not_gate(y, a);
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input a;
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output y;
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always @ (a)begin
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if(a==1'b1)begin
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y=0'b0;
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end
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else
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y=1'b1;
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end
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endmodule |