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2022-03-08 15:07:02 +01:00

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Systemverilog

import sr_flipflop::*;
package d_flipflop (
output dq, dq_compl
input d, clk,
);
nand(tmp0, d, clk);
nand(tmp1, clk, tmp0);
sr_flipflop(dq, dq_compl, tmp0, tmp1);
endpackage