Erick
50 lines
1.3 KiB
Systemverilog
50 lines
1.3 KiB
Systemverilog
import ram512::*;
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package ram4096 (
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input [4095:0]in;
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input [11:0]addr;
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input load;
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input clk
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output [4095:0]out;
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);
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wire [511:0] [511:0] in0 = in;
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wire [1023:511] [511:0] in1 = in;
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wire [1535:1023] [511:0] in2 = in;
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wire [2047:1535] [511:0] in3 = in;
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wire [2559:2047] [511:0] in4 = in;
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wire [3071:2559] [511:0] in5 = in;
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wire [3583:3071] [511:0] in6 = in;
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wire [4095:3583] [511:0] in7 = in;
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wire [11:0] [8:0] addr0 = in;
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wire [0:11] [8:0] addr1 = in;
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wire [511:0]out0;
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wire [511:0]out1;
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wire [511:0]out2;
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wire [511:0]out3;
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wire [511:0]out4;
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wire [511:0]out5;
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wire [511:0]out6;
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wire [511:0]out7;
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ram512 clstr0(in0, addr0, load, clk, out0);
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ram512 clstr1(in1, addr0, load, clk, out1);
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ram512 clstr2(in2, addr0, load, clk, out2);
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ram512 clstr3(in3, addr0, load, clk, out3);
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ram512 clstr4(in4, addr1, load, clk, out4);
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ram512 clstr5(in5, addr1, load, clk, out5);
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ram512 clstr6(in6, addr1, load, clk, out6);
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ram512 clstr7(in7, addr1, load, clk, out7);
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wire [511:0] [511:0] out0 = out;
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wire [511:0] [1023:511] out1 = out;
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wire [511:0] [1535:1023] out2 = out;
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wire [511:0] [2047:1535] out3 = out;
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wire [511:0] [2559:2047] out4 = out;
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wire [511:0] [3071:2559] out5 = out;
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wire [511:0] [3583:3071] out6 = out;
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wire [511:0] [4095:3583] out7 = out;
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endpackage |