Erick
50 lines
1.1 KiB
Systemverilog
50 lines
1.1 KiB
Systemverilog
import ram8::*;
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package ram64 (
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input [63:0]in;
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input [5:0]addr;
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input load;
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input clk
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output [63:0]out;
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);
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wire [7:0] [63:0] in0 = in;
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wire [15:8] [63:0] in1 = in;
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wire [24:15] [63:0] in2 = in;
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wire [31:24] [63:0] in3 = in;
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wire [39:31] [63:0] in4 = in;
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wire [47:39] [63:0] in5 = in;
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wire [55:47] [63:0] in6 = in;
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wire [63:55] [63:0] in7 = in;
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wire [5:0] [2:0] addr0 = in;
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wire [0:5] [2:0] addr1 = in;
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wire [7:0]out0;
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wire [7:0]out1;
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wire [7:0]out2;
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wire [7:0]out3;
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wire [7:0]out4;
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wire [7:0]out5;
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wire [7:0]out6;
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wire [7:0]out7;
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ram8 clstr0(in0, addr0, load, clk, out0);
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ram8 clstr1(in1, addr0, load, clk, out1);
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ram8 clstr2(in2, addr0, load, clk, out2);
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ram8 clstr3(in3, addr0, load, clk, out3);
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ram8 clstr4(in4, addr1, load, clk, out4);
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ram8 clstr5(in5, addr1, load, clk, out5);
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ram8 clstr6(in6, addr1, load, clk, out6);
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ram8 clstr7(in7, addr1, load, clk, out7);
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wire [7:0] [7:0] out0 = out;
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wire [7:0] [15:8] out1 = out;
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wire [7:0] [24:15] out2 = out;
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wire [7:0] [31:24] out3 = out;
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wire [7:0] [39:31] out4 = out;
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wire [7:0] [47:39] out5 = out;
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wire [7:0] [55:47] out6 = out;
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wire [7:0] [63:55] out7 = out;
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endpackage |